0001 STMicroelectronics stih4xx platforms
0002
0003 - sti-vtg: video timing generator
0004 Required properties:
0005 - compatible: "st,vtg"
0006 - reg: Physical base address of the IP registers and length of memory mapped region.
0007 Optional properties:
0008 - interrupts : VTG interrupt number to the CPU.
0009 - st,slave: phandle on a slave vtg
0010
0011 - sti-vtac: video timing advanced inter dye communication Rx and TX
0012 Required properties:
0013 - compatible: "st,vtac-main" or "st,vtac-aux"
0014 - reg: Physical base address of the IP registers and length of memory mapped region.
0015 - clocks: from common clock binding: handle hardware IP needed clocks, the
0016 number of clocks may depend of the SoC type.
0017 See ../clocks/clock-bindings.txt for details.
0018 - clock-names: names of the clocks listed in clocks property in the same
0019 order.
0020
0021 - sti-display-subsystem: Master device for DRM sub-components
0022 This device must be the parent of all the sub-components and is responsible
0023 of bind them.
0024 Required properties:
0025 - compatible: "st,sti-display-subsystem"
0026 - ranges: to allow probing of subdevices
0027
0028 - sti-compositor: frame compositor engine
0029 must be a child of sti-display-subsystem
0030 Required properties:
0031 - compatible: "st,stih<chip>-compositor"
0032 - reg: Physical base address of the IP registers and length of memory mapped region.
0033 - clocks: from common clock binding: handle hardware IP needed clocks, the
0034 number of clocks may depend of the SoC type.
0035 See ../clocks/clock-bindings.txt for details.
0036 - clock-names: names of the clocks listed in clocks property in the same
0037 order.
0038 - resets: resets to be used by the device
0039 See ../reset/reset.txt for details.
0040 - reset-names: names of the resets listed in resets property in the same
0041 order.
0042 - st,vtg: phandle(s) on vtg device (main and aux) nodes.
0043
0044 - sti-tvout: video out hardware block
0045 must be a child of sti-display-subsystem
0046 Required properties:
0047 - compatible: "st,stih<chip>-tvout"
0048 - reg: Physical base address of the IP registers and length of memory mapped region.
0049 - reg-names: names of the mapped memory regions listed in regs property in
0050 the same order.
0051 - resets: resets to be used by the device
0052 See ../reset/reset.txt for details.
0053 - reset-names: names of the resets listed in resets property in the same
0054 order.
0055
0056 - sti-hdmi: hdmi output block
0057 must be a child of sti-display-subsystem
0058 Required properties:
0059 - compatible: "st,stih<chip>-hdmi";
0060 - reg: Physical base address of the IP registers and length of memory mapped region.
0061 - reg-names: names of the mapped memory regions listed in regs property in
0062 the same order.
0063 - interrupts : HDMI interrupt number to the CPU.
0064 - interrupt-names: names of the interrupts listed in interrupts property in
0065 the same order
0066 - clocks: from common clock binding: handle hardware IP needed clocks, the
0067 number of clocks may depend of the SoC type.
0068 - clock-names: names of the clocks listed in clocks property in the same
0069 order.
0070 - ddc: phandle of an I2C controller used for DDC EDID probing
0071
0072 sti-hda:
0073 Required properties:
0074 must be a child of sti-display-subsystem
0075 - compatible: "st,stih<chip>-hda"
0076 - reg: Physical base address of the IP registers and length of memory mapped region.
0077 - reg-names: names of the mapped memory regions listed in regs property in
0078 the same order.
0079 - clocks: from common clock binding: handle hardware IP needed clocks, the
0080 number of clocks may depend of the SoC type.
0081 See ../clocks/clock-bindings.txt for details.
0082 - clock-names: names of the clocks listed in clocks property in the same
0083 order.
0084
0085 sti-dvo:
0086 Required properties:
0087 must be a child of sti-display-subsystem
0088 - compatible: "st,stih<chip>-dvo"
0089 - reg: Physical base address of the IP registers and length of memory mapped region.
0090 - reg-names: names of the mapped memory regions listed in regs property in
0091 the same order.
0092 - clocks: from common clock binding: handle hardware IP needed clocks, the
0093 number of clocks may depend of the SoC type.
0094 See ../clocks/clock-bindings.txt for details.
0095 - clock-names: names of the clocks listed in clocks property in the same
0096 order.
0097 - pinctrl-0: pin control handle
0098 - pinctrl-names: names of the pin control states to use
0099 - sti,panel: phandle of the panel connected to the DVO output
0100
0101 sti-hqvdp:
0102 must be a child of sti-display-subsystem
0103 Required properties:
0104 - compatible: "st,stih<chip>-hqvdp"
0105 - reg: Physical base address of the IP registers and length of memory mapped region.
0106 - clocks: from common clock binding: handle hardware IP needed clocks, the
0107 number of clocks may depend of the SoC type.
0108 See ../clocks/clock-bindings.txt for details.
0109 - clock-names: names of the clocks listed in clocks property in the same
0110 order.
0111 - resets: resets to be used by the device
0112 See ../reset/reset.txt for details.
0113 - reset-names: names of the resets listed in resets property in the same
0114 order.
0115 - st,vtg: phandle on vtg main device node.
0116
0117 Example:
0118
0119 / {
0120 ...
0121
0122 vtg_main_slave: sti-vtg-main-slave@fe85a800 {
0123 compatible = "st,vtg";
0124 reg = <0xfe85A800 0x300>;
0125 interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
0126 };
0127
0128 vtg_main: sti-vtg-main-master@fd348000 {
0129 compatible = "st,vtg";
0130 reg = <0xfd348000 0x400>;
0131 st,slave = <&vtg_main_slave>;
0132 };
0133
0134 vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
0135 compatible = "st,vtg";
0136 reg = <0xfe858200 0x300>;
0137 interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
0138 };
0139
0140 vtg_aux: sti-vtg-aux-master@fd348400 {
0141 compatible = "st,vtg";
0142 reg = <0xfd348400 0x400>;
0143 st,slave = <&vtg_aux_slave>;
0144 };
0145
0146
0147 sti-vtac-rx-main@fee82800 {
0148 compatible = "st,vtac-main";
0149 reg = <0xfee82800 0x200>;
0150 clock-names = "vtac";
0151 clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
0152 };
0153
0154 sti-vtac-rx-aux@fee82a00 {
0155 compatible = "st,vtac-aux";
0156 reg = <0xfee82a00 0x200>;
0157 clock-names = "vtac";
0158 clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
0159 };
0160
0161 sti-vtac-tx-main@fd349000 {
0162 compatible = "st,vtac-main";
0163 reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
0164 clock-names = "vtac";
0165 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
0166 };
0167
0168 sti-vtac-tx-aux@fd349200 {
0169 compatible = "st,vtac-aux";
0170 reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
0171 clock-names = "vtac";
0172 clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
0173 };
0174
0175 sti-display-subsystem {
0176 compatible = "st,sti-display-subsystem";
0177 ranges;
0178
0179 sti-compositor@fd340000 {
0180 compatible = "st,stih416-compositor";
0181 reg = <0xfd340000 0x1000>;
0182 clock-names = "compo_main", "compo_aux",
0183 "pix_main", "pix_aux";
0184 clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
0185 <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
0186 reset-names = "compo-main", "compo-aux";
0187 resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
0188 st,vtg = <&vtg_main>, <&vtg_aux>;
0189 };
0190
0191 sti-tvout@fe000000 {
0192 compatible = "st,stih416-tvout";
0193 reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
0194 reg-names = "tvout-reg", "hda-reg", "syscfg";
0195 reset-names = "tvout";
0196 resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
0197 };
0198
0199 sti-hdmi@fe85c000 {
0200 compatible = "st,stih416-hdmi";
0201 reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
0202 reg-names = "hdmi-reg", "syscfg";
0203 interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
0204 interrupt-names = "irq";
0205 clock-names = "pix", "tmds", "phy", "audio";
0206 clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
0207 };
0208
0209 sti-hda@fe85a000 {
0210 compatible = "st,stih416-hda";
0211 reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
0212 reg-names = "hda-reg", "video-dacs-ctrl";
0213 clock-names = "pix", "hddac";
0214 clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
0215 };
0216
0217 sti-dvo@8d00400 {
0218 compatible = "st,stih407-dvo";
0219 reg = <0x8d00400 0x200>;
0220 reg-names = "dvo-reg";
0221 clock-names = "dvo_pix", "dvo",
0222 "main_parent", "aux_parent";
0223 clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
0224 <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_dvo>;
0227 sti,panel = <&panel_dvo>;
0228 };
0229
0230 sti-hqvdp@9c000000 {
0231 compatible = "st,stih407-hqvdp";
0232 reg = <0x9C00000 0x100000>;
0233 clock-names = "hqvdp", "pix_main";
0234 clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
0235 reset-names = "hqvdp";
0236 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
0237 st,vtg = <&vtg_main>;
0238 };
0239 };
0240 ...
0241 };
