0001 ARC PGU
0002
0003 This is a display controller found on several development boards produced
0004 by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
0005 framebuffer and sends it to a single digital encoder (usually HDMI).
0006
0007 Required properties:
0008 - compatible: "snps,arcpgu"
0009 - reg: Physical base address and length of the controller's registers.
0010 - clocks: A list of phandle + clock-specifier pairs, one for each
0011 entry in 'clock-names'.
0012 - clock-names: A list of clock names. For ARC PGU it should contain:
0013 - "pxlclk" for the clock feeding the output PLL of the controller.
0014
0015 Required sub-nodes:
0016 - port: The PGU connection to an encoder chip.
0017
0018 Example:
0019
0020 / {
0021 ...
0022
0023 pgu@XXXXXXXX {
0024 compatible = "snps,arcpgu";
0025 reg = <0xXXXXXXXX 0x400>;
0026 clocks = <&clock_node>;
0027 clock-names = "pxlclk";
0028
0029 port {
0030 pgu_output: endpoint {
0031 remote-endpoint = <&hdmi_enc_input>;
0032 };
0033 };
0034 };
0035 };
