0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
0008
0009 maintainers:
0010 - Inki Dae <inki.dae@samsung.com>
0011 - Seung-Woo Kim <sw0312.kim@samsung.com>
0012 - Kyungmin Park <kyungmin.park@samsung.com>
0013 - Krzysztof Kozlowski <krzk@kernel.org>
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - samsung,s3c2443-fimd
0019 - samsung,s3c6400-fimd
0020 - samsung,s5pv210-fimd
0021 - samsung,exynos3250-fimd
0022 - samsung,exynos4210-fimd
0023 - samsung,exynos5250-fimd
0024 - samsung,exynos5420-fimd
0025
0026 '#address-cells':
0027 const: 1
0028
0029 clocks:
0030 minItems: 2
0031 maxItems: 2
0032
0033 clock-names:
0034 items:
0035 - const: sclk_fimd
0036 - const: fimd
0037
0038 display-timings:
0039 $ref: ../panel/display-timings.yaml#
0040
0041 i80-if-timings:
0042 type: object
0043 description: |
0044 Timing configuration for lcd i80 interface support.
0045 The parameters are defined as::
0046 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
0047 : : : : :
0048 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
0049 | cs-setup+1 | : : :
0050 |<---------->| : : :
0051 Chip Select ???????????????|____________:____________:____________|??
0052 | wr-setup+1 | | wr-hold+1 |
0053 |<---------->| |<---------->|
0054 Write Enable ????????????????????????????|____________|???????????????
0055 | wr-active+1|
0056 |<---------->|
0057 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
0058
0059 properties:
0060 cs-setup:
0061 $ref: /schemas/types.yaml#/definitions/uint32
0062 description:
0063 Clock cycles for the active period of address signal is enabled until
0064 chip select is enabled.
0065 default: 0
0066
0067 wr-active:
0068 $ref: /schemas/types.yaml#/definitions/uint32
0069 description:
0070 Clock cycles for the active period of CS is enabled.
0071 default: 1
0072
0073 wr-hold:
0074 $ref: /schemas/types.yaml#/definitions/uint32
0075 description:
0076 Clock cycles for the active period of CS is disabled until write
0077 signal is disabled.
0078 default: 0
0079
0080 wr-setup:
0081 $ref: /schemas/types.yaml#/definitions/uint32
0082 description:
0083 Clock cycles for the active period of CS signal is enabled until
0084 write signal is enabled.
0085 default: 0
0086
0087 iommus:
0088 minItems: 1
0089 maxItems: 2
0090
0091 iommu-names:
0092 items:
0093 - const: m0
0094 - const: m1
0095
0096 interrupts:
0097 items:
0098 - description: FIFO level
0099 - description: VSYNC
0100 - description: LCD system
0101
0102 interrupt-names:
0103 items:
0104 - const: fifo
0105 - const: vsync
0106 - const: lcd_sys
0107
0108 power-domains:
0109 maxItems: 1
0110
0111 reg:
0112 maxItems: 1
0113
0114 samsung,invert-vden:
0115 type: boolean
0116 description:
0117 Video enable signal is inverted.
0118
0119 samsung,invert-vclk:
0120 type: boolean
0121 description:
0122 Video clock signal is inverted.
0123
0124 samsung,sysreg:
0125 $ref: /schemas/types.yaml#/definitions/phandle
0126 description:
0127 Phandle to System Register syscon.
0128
0129 '#size-cells':
0130 const: 0
0131
0132 patternProperties:
0133 "^port@[0-4]+$":
0134 $ref: /schemas/graph.yaml#/properties/port
0135 description: |
0136 Contains ports with port with index::
0137 0 - for CAMIF0 input,
0138 1 - for CAMIF1 input,
0139 2 - for CAMIF2 input,
0140 3 - for parallel output,
0141 4 - for write-back interface
0142
0143 required:
0144 - compatible
0145 - clocks
0146 - clock-names
0147 - interrupts
0148 - interrupt-names
0149 - reg
0150
0151 allOf:
0152 - if:
0153 properties:
0154 compatible:
0155 contains:
0156 const: samsung,exynos5420-fimd
0157 then:
0158 properties:
0159 iommus:
0160 minItems: 2
0161 maxItems: 2
0162
0163 additionalProperties: false
0164
0165 examples:
0166 - |
0167 #include <dt-bindings/clock/exynos4.h>
0168
0169 fimd@11c00000 {
0170 compatible = "samsung,exynos4210-fimd";
0171 interrupt-parent = <&combiner>;
0172 reg = <0x11c00000 0x20000>;
0173 interrupt-names = "fifo", "vsync", "lcd_sys";
0174 interrupts = <11 0>, <11 1>, <11 2>;
0175 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
0176 clock-names = "sclk_fimd", "fimd";
0177 power-domains = <&pd_lcd0>;
0178 iommus = <&sysmmu_fimd0>;
0179 samsung,sysreg = <&sys_reg>;
0180
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183
0184 samsung,invert-vden;
0185 samsung,invert-vclk;
0186
0187 pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
0188 pinctrl-names = "default";
0189
0190 port@3 {
0191 reg = <3>;
0192
0193 fimd_dpi_ep: endpoint {
0194 remote-endpoint = <&lcd_ep>;
0195 };
0196 };
0197 };
