0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
0008
0009 maintainers:
0010 - Inki Dae <inki.dae@samsung.com>
0011 - Seung-Woo Kim <sw0312.kim@samsung.com>
0012 - Kyungmin Park <kyungmin.park@samsung.com>
0013 - Krzysztof Kozlowski <krzk@kernel.org>
0014
0015 description: |
0016 DECON (Display and Enhancement Controller) is the Display Controller for the
0017 Exynos7 series of SoCs which transfers the image data from a video memory
0018 buffer to an external LCD interface.
0019
0020 properties:
0021 compatible:
0022 const: samsung,exynos7-decon
0023
0024 clocks:
0025 minItems: 4
0026 maxItems: 4
0027
0028 clock-names:
0029 items:
0030 - const: pclk_decon0
0031 - const: aclk_decon0
0032 - const: decon0_eclk
0033 - const: decon0_vclk
0034
0035 display-timings:
0036 $ref: ../panel/display-timings.yaml#
0037
0038 i80-if-timings:
0039 type: object
0040 description: timing configuration for lcd i80 interface support
0041 properties:
0042 cs-setup:
0043 $ref: /schemas/types.yaml#/definitions/uint32
0044 description:
0045 Clock cycles for the active period of address signal is enabled until
0046 chip select is enabled.
0047 default: 0
0048
0049 wr-active:
0050 $ref: /schemas/types.yaml#/definitions/uint32
0051 description:
0052 Clock cycles for the active period of CS is enabled.
0053 default: 1
0054
0055 wr-hold:
0056 $ref: /schemas/types.yaml#/definitions/uint32
0057 description:
0058 Clock cycles for the active period of CS is disabled until write
0059 signal is disabled.
0060 default: 0
0061
0062 wr-setup:
0063 $ref: /schemas/types.yaml#/definitions/uint32
0064 description:
0065 Clock cycles for the active period of CS signal is enabled until
0066 write signal is enabled.
0067 default: 0
0068
0069 interrupts:
0070 items:
0071 - description: FIFO level
0072 - description: VSYNC
0073 - description: LCD system
0074
0075 interrupt-names:
0076 items:
0077 - const: fifo
0078 - const: vsync
0079 - const: lcd_sys
0080
0081 power-domains:
0082 maxItems: 1
0083
0084 reg:
0085 maxItems: 1
0086
0087 required:
0088 - compatible
0089 - clocks
0090 - clock-names
0091 - interrupts
0092 - interrupt-names
0093 - reg
0094
0095 additionalProperties: false
0096
0097 examples:
0098 - |
0099 #include <dt-bindings/clock/exynos7-clk.h>
0100 #include <dt-bindings/interrupt-controller/arm-gic.h>
0101
0102 display-controller@13930000 {
0103 compatible = "samsung,exynos7-decon";
0104 reg = <0x13930000 0x1000>;
0105 interrupt-names = "fifo", "vsync", "lcd_sys";
0106 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0109 clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
0110 <&clock_disp 101>, /* ACLK_DECON_INT */
0111 <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
0112 <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
0113 clock-names = "pclk_decon0",
0114 "aclk_decon0",
0115 "decon0_eclk",
0116 "decon0_vclk";
0117 pinctrl-0 = <&lcd_clk &pwm1_out>;
0118 pinctrl-names = "default";
0119 };
