0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
0008
0009 maintainers:
0010 - Inki Dae <inki.dae@samsung.com>
0011 - Seung-Woo Kim <sw0312.kim@samsung.com>
0012 - Kyungmin Park <kyungmin.park@samsung.com>
0013 - Krzysztof Kozlowski <krzk@kernel.org>
0014
0015 description: |
0016 DECON (Display and Enhancement Controller) is the Display Controller for the
0017 Exynos5433 series of SoCs which transfers the image data from a video memory
0018 buffer to an external LCD interface.
0019
0020 properties:
0021 compatible:
0022 enum:
0023 - samsung,exynos5433-decon
0024 - samsung,exynos5433-decon-tv
0025
0026 clocks:
0027 minItems: 11
0028 maxItems: 11
0029
0030 clock-names:
0031 items:
0032 - const: pclk
0033 - const: aclk_decon
0034 - const: aclk_smmu_decon0x
0035 - const: aclk_xiu_decon0x
0036 - const: pclk_smmu_decon0x
0037 - const: aclk_smmu_decon1x
0038 - const: aclk_xiu_decon1x
0039 - const: pclk_smmu_decon1x
0040 - const: sclk_decon_vclk
0041 - const: sclk_decon_eclk
0042 - const: dsd
0043
0044 interrupts:
0045 minItems: 3
0046 maxItems: 4
0047 description: |
0048 Interrupts depend on mode of work:
0049 - video mode: vsync
0050 - command mode: lcd_sys
0051 - command mode with software trigger: lcd_sys, te
0052
0053 interrupt-names:
0054 minItems: 3
0055 items:
0056 - const: fifo
0057 - const: vsync
0058 - const: lcd_sys
0059 - const: te
0060
0061 iommus:
0062 minItems: 2
0063 maxItems: 2
0064
0065 iommu-names:
0066 items:
0067 - const: m0
0068 - const: m1
0069
0070 ports:
0071 $ref: /schemas/graph.yaml#/properties/ports
0072 description:
0073 Contains a port which is connected to mic node.
0074
0075 power-domains:
0076 maxItems: 1
0077
0078 reg:
0079 maxItems: 1
0080
0081 samsung,disp-sysreg:
0082 $ref: /schemas/types.yaml#/definitions/phandle
0083 description:
0084 Phandle to DISP system controller interface.
0085
0086 required:
0087 - compatible
0088 - clocks
0089 - clock-names
0090 - interrupts
0091 - interrupt-names
0092 - ports
0093 - reg
0094
0095 additionalProperties: false
0096
0097 examples:
0098 - |
0099 #include <dt-bindings/clock/exynos5433.h>
0100 #include <dt-bindings/interrupt-controller/arm-gic.h>
0101
0102 display-controller@13800000 {
0103 compatible = "samsung,exynos5433-decon";
0104 reg = <0x13800000 0x2104>;
0105 clocks = <&cmu_disp CLK_PCLK_DECON>,
0106 <&cmu_disp CLK_ACLK_DECON>,
0107 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
0108 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
0109 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
0110 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
0111 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
0112 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
0113 <&cmu_disp CLK_SCLK_DECON_VCLK>,
0114 <&cmu_disp CLK_SCLK_DECON_ECLK>,
0115 <&cmu_disp CLK_SCLK_DSD>;
0116 clock-names = "pclk",
0117 "aclk_decon",
0118 "aclk_smmu_decon0x",
0119 "aclk_xiu_decon0x",
0120 "pclk_smmu_decon0x",
0121 "aclk_smmu_decon1x",
0122 "aclk_xiu_decon1x",
0123 "pclk_smmu_decon1x",
0124 "sclk_decon_vclk",
0125 "sclk_decon_eclk",
0126 "dsd";
0127 power-domains = <&pd_disp>;
0128 interrupt-names = "fifo", "vsync", "lcd_sys";
0129 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0130 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0132 samsung,disp-sysreg = <&syscon_disp>;
0133 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
0134 iommu-names = "m0", "m1";
0135
0136 ports {
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139
0140 port@0 {
0141 reg = <0>;
0142 decon_to_mic: endpoint {
0143 remote-endpoint = <&mic_to_decon>;
0144 };
0145 };
0146 };
0147 };
