0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SoC display controller (VOP2)
0008
0009 description:
0010 VOP2 (Video Output Processor v2) is the display controller for the Rockchip
0011 series of SoCs which transfers the image data from a video memory
0012 buffer to an external LCD interface.
0013
0014 maintainers:
0015 - Sandy Huang <hjc@rock-chips.com>
0016 - Heiko Stuebner <heiko@sntech.de>
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - rockchip,rk3566-vop
0022 - rockchip,rk3568-vop
0023
0024 reg:
0025 items:
0026 - description:
0027 Must contain one entry corresponding to the base address and length
0028 of the register space.
0029 - description:
0030 Can optionally contain a second entry corresponding to
0031 the CRTC gamma LUT address.
0032
0033 reg-names:
0034 items:
0035 - const: vop
0036 - const: gamma-lut
0037
0038 interrupts:
0039 maxItems: 1
0040 description:
0041 The VOP interrupt is shared by several interrupt sources, such as
0042 frame start (VSYNC), line flag and other status interrupts.
0043
0044 clocks:
0045 items:
0046 - description: Clock for ddr buffer transfer.
0047 - description: Clock for the ahb bus to R/W the phy regs.
0048 - description: Pixel clock for video port 0.
0049 - description: Pixel clock for video port 1.
0050 - description: Pixel clock for video port 2.
0051
0052 clock-names:
0053 items:
0054 - const: aclk
0055 - const: hclk
0056 - const: dclk_vp0
0057 - const: dclk_vp1
0058 - const: dclk_vp2
0059
0060 rockchip,grf:
0061 $ref: /schemas/types.yaml#/definitions/phandle
0062 description:
0063 Phandle to GRF regs used for misc control
0064
0065 ports:
0066 $ref: /schemas/graph.yaml#/properties/ports
0067
0068 properties:
0069 port@0:
0070 $ref: /schemas/graph.yaml#/properties/port
0071 description:
0072 Output endpoint of VP0
0073
0074 port@1:
0075 $ref: /schemas/graph.yaml#/properties/port
0076 description:
0077 Output endpoint of VP1
0078
0079 port@2:
0080 $ref: /schemas/graph.yaml#/properties/port
0081 description:
0082 Output endpoint of VP2
0083
0084 iommus:
0085 maxItems: 1
0086
0087 power-domains:
0088 maxItems: 1
0089
0090 required:
0091 - compatible
0092 - reg
0093 - reg-names
0094 - interrupts
0095 - clocks
0096 - clock-names
0097 - ports
0098
0099 additionalProperties: false
0100
0101 examples:
0102 - |
0103 #include <dt-bindings/clock/rk3568-cru.h>
0104 #include <dt-bindings/interrupt-controller/arm-gic.h>
0105 #include <dt-bindings/power/rk3568-power.h>
0106 bus {
0107 #address-cells = <2>;
0108 #size-cells = <2>;
0109 vop: vop@fe040000 {
0110 compatible = "rockchip,rk3568-vop";
0111 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
0112 reg-names = "vop", "gamma-lut";
0113 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0114 clocks = <&cru ACLK_VOP>,
0115 <&cru HCLK_VOP>,
0116 <&cru DCLK_VOP0>,
0117 <&cru DCLK_VOP1>,
0118 <&cru DCLK_VOP2>;
0119 clock-names = "aclk",
0120 "hclk",
0121 "dclk_vp0",
0122 "dclk_vp1",
0123 "dclk_vp2";
0124 power-domains = <&power RK3568_PD_VO>;
0125 iommus = <&vop_mmu>;
0126 vop_out: ports {
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129 vp0: port@0 {
0130 reg = <0>;
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133 };
0134 vp1: port@1 {
0135 reg = <1>;
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138 };
0139 vp2: port@2 {
0140 reg = <2>;
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143 };
0144 };
0145 };
0146 };
