0001 Rockchip RK3288 LVDS interface
0002 ================================
0003
0004 Required properties:
0005 - compatible: matching the soc type, one of
0006 - "rockchip,rk3288-lvds";
0007 - "rockchip,px30-lvds";
0008
0009 - reg: physical base address of the controller and length
0010 of memory mapped region.
0011 - clocks: must include clock specifiers corresponding to entries in the
0012 clock-names property.
0013 - clock-names: must contain "pclk_lvds"
0014
0015 - avdd1v0-supply: regulator phandle for 1.0V analog power
0016 - avdd1v8-supply: regulator phandle for 1.8V analog power
0017 - avdd3v3-supply: regulator phandle for 3.3V analog power
0018
0019 - rockchip,grf: phandle to the general register files syscon
0020 - rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
0021
0022 - phys: LVDS/DSI DPHY (px30 only)
0023 - phy-names: name of the PHY, must be "dphy" (px30 only)
0024
0025 Optional properties:
0026 - pinctrl-names: must contain a "lcdc" entry.
0027 - pinctrl-0: pin control group to be used for this controller.
0028
0029 Required nodes:
0030
0031 The lvds has two video ports as described by
0032 Documentation/devicetree/bindings/media/video-interfaces.txt
0033 Their connections are modeled using the OF graph bindings specified in
0034 Documentation/devicetree/bindings/graph.txt.
0035
0036 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
0037 - video port 1 for either a panel or subsequent encoder
0038
0039 Example:
0040
0041 lvds_panel: lvds-panel {
0042 compatible = "auo,b101ean01";
0043 enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
0044 data-mapping = "jeida-24";
0045
0046 ports {
0047 panel_in_lvds: endpoint {
0048 remote-endpoint = <&lvds_out_panel>;
0049 };
0050 };
0051 };
0052
0053 For Rockchip RK3288:
0054
0055 lvds: lvds@ff96c000 {
0056 compatible = "rockchip,rk3288-lvds";
0057 rockchip,grf = <&grf>;
0058 reg = <0xff96c000 0x4000>;
0059 clocks = <&cru PCLK_LVDS_PHY>;
0060 clock-names = "pclk_lvds";
0061 pinctrl-names = "lcdc";
0062 pinctrl-0 = <&lcdc_ctl>;
0063 avdd1v0-supply = <&vdd10_lcd>;
0064 avdd1v8-supply = <&vcc18_lcd>;
0065 avdd3v3-supply = <&vcca_33>;
0066 rockchip,output = "rgb";
0067 ports {
0068 #address-cells = <1>;
0069 #size-cells = <0>;
0070
0071 lvds_in: port@0 {
0072 reg = <0>;
0073
0074 lvds_in_vopb: endpoint@0 {
0075 reg = <0>;
0076 remote-endpoint = <&vopb_out_lvds>;
0077 };
0078 lvds_in_vopl: endpoint@1 {
0079 reg = <1>;
0080 remote-endpoint = <&vopl_out_lvds>;
0081 };
0082 };
0083
0084 lvds_out: port@1 {
0085 reg = <1>;
0086
0087 lvds_out_panel: endpoint {
0088 remote-endpoint = <&panel_in_lvds>;
0089 };
0090 };
0091 };
0092 };
