0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3066-hdmi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip rk3066 HDMI controller
0008
0009 maintainers:
0010 - Sandy Huang <hjc@rock-chips.com>
0011 - Heiko Stuebner <heiko@sntech.de>
0012
0013 properties:
0014 compatible:
0015 const: rockchip,rk3066-hdmi
0016
0017 reg:
0018 maxItems: 1
0019
0020 interrupts:
0021 maxItems: 1
0022
0023 clocks:
0024 maxItems: 1
0025
0026 clock-names:
0027 const: hclk
0028
0029 power-domains:
0030 maxItems: 1
0031
0032 rockchip,grf:
0033 $ref: /schemas/types.yaml#/definitions/phandle
0034 description:
0035 This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
0036
0037 ports:
0038 $ref: /schemas/graph.yaml#/properties/ports
0039
0040 properties:
0041 port@0:
0042 $ref: /schemas/graph.yaml#/properties/port
0043 description:
0044 Port node with two endpoints, numbered 0 and 1,
0045 connected respectively to vop0 and vop1.
0046
0047 port@1:
0048 $ref: /schemas/graph.yaml#/properties/port
0049 description:
0050 Port node with one endpoint connected to a hdmi-connector node.
0051
0052 required:
0053 - port@0
0054 - port@1
0055
0056 required:
0057 - compatible
0058 - reg
0059 - interrupts
0060 - clocks
0061 - clock-names
0062 - pinctrl-0
0063 - pinctrl-names
0064 - power-domains
0065 - rockchip,grf
0066 - ports
0067
0068 additionalProperties: false
0069
0070 examples:
0071 - |
0072 #include <dt-bindings/clock/rk3066a-cru.h>
0073 #include <dt-bindings/interrupt-controller/arm-gic.h>
0074 #include <dt-bindings/pinctrl/rockchip.h>
0075 #include <dt-bindings/power/rk3066-power.h>
0076 hdmi: hdmi@10116000 {
0077 compatible = "rockchip,rk3066-hdmi";
0078 reg = <0x10116000 0x2000>;
0079 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0080 clocks = <&cru HCLK_HDMI>;
0081 clock-names = "hclk";
0082 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
0083 pinctrl-names = "default";
0084 power-domains = <&power RK3066_PD_VIO>;
0085 rockchip,grf = <&grf>;
0086
0087 ports {
0088 #address-cells = <1>;
0089 #size-cells = <0>;
0090 hdmi_in: port@0 {
0091 reg = <0>;
0092 #address-cells = <1>;
0093 #size-cells = <0>;
0094 hdmi_in_vop0: endpoint@0 {
0095 reg = <0>;
0096 remote-endpoint = <&vop0_out_hdmi>;
0097 };
0098 hdmi_in_vop1: endpoint@1 {
0099 reg = <1>;
0100 remote-endpoint = <&vop1_out_hdmi>;
0101 };
0102 };
0103 hdmi_out: port@1 {
0104 reg = <1>;
0105 hdmi_out_con: endpoint {
0106 remote-endpoint = <&hdmi_con_in>;
0107 };
0108 };
0109 };
0110 };
0111
0112 pinctrl {
0113 hdmi {
0114 hdmi_hpd: hdmi-hpd {
0115 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
0116 };
0117 hdmii2c_xfer: hdmii2c-xfer {
0118 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
0119 <0 RK_PA2 1 &pcfg_pull_none>;
0120 };
0121 };
0122 };
