0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip DWC HDMI TX Encoder
0008
0009 maintainers:
0010 - Mark Yao <markyao0591@gmail.com>
0011
0012 description: |
0013 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
0014 with a companion PHY IP.
0015
0016 allOf:
0017 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - rockchip,rk3228-dw-hdmi
0023 - rockchip,rk3288-dw-hdmi
0024 - rockchip,rk3328-dw-hdmi
0025 - rockchip,rk3399-dw-hdmi
0026 - rockchip,rk3568-dw-hdmi
0027
0028 reg-io-width:
0029 const: 4
0030
0031 avdd-0v9-supply:
0032 description:
0033 A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
0034 varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
0035 HDMI_AVDD_1V0.
0036
0037 avdd-1v8-supply:
0038 description:
0039 A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
0040 SoC usually is HDMI_TX_AVDD_1V8.
0041
0042 clocks:
0043 minItems: 2
0044 items:
0045 - {}
0046 - {}
0047 # The next three clocks are all optional, but shall be specified in this
0048 # order when present.
0049 - description: The HDMI CEC controller main clock
0050 - description: Power for GRF IO
0051 - description: External clock for some HDMI PHY (old clock name, deprecated)
0052 - description: External clock for some HDMI PHY (new name)
0053
0054 clock-names:
0055 minItems: 2
0056 items:
0057 - {}
0058 - {}
0059 - enum:
0060 - cec
0061 - grf
0062 - vpll
0063 - ref
0064 - enum:
0065 - grf
0066 - vpll
0067 - ref
0068 - enum:
0069 - vpll
0070 - ref
0071
0072 ddc-i2c-bus:
0073 $ref: /schemas/types.yaml#/definitions/phandle
0074 description:
0075 The HDMI DDC bus can be connected to either a system I2C master or the
0076 functionally-reduced I2C master contained in the DWC HDMI. When connected
0077 to a system I2C master this property contains a phandle to that I2C
0078 master controller.
0079
0080 phys:
0081 maxItems: 1
0082 description: The HDMI PHY
0083
0084 phy-names:
0085 const: hdmi
0086
0087 pinctrl-names:
0088 description:
0089 The unwedge pinctrl entry shall drive the DDC SDA line low. This is
0090 intended to work around a hardware errata that can cause the DDC I2C
0091 bus to be wedged.
0092 minItems: 1
0093 items:
0094 - const: default
0095 - const: unwedge
0096
0097 ports:
0098 $ref: /schemas/graph.yaml#/properties/ports
0099
0100 patternProperties:
0101 "^port(@0)?$":
0102 $ref: /schemas/graph.yaml#/properties/port
0103 description: Input of the DWC HDMI TX
0104 properties:
0105 endpoint:
0106 description: Connection to the VOP
0107 endpoint@0:
0108 description: Connection to the VOPB
0109 endpoint@1:
0110 description: Connection to the VOPL
0111 properties:
0112 port@1:
0113 $ref: /schemas/graph.yaml#/properties/port
0114 description: Output of the DWC HDMI TX
0115
0116 rockchip,grf:
0117 $ref: /schemas/types.yaml#/definitions/phandle
0118 description:
0119 phandle to the GRF to mux vopl/vopb.
0120
0121 required:
0122 - compatible
0123 - reg
0124 - reg-io-width
0125 - clocks
0126 - clock-names
0127 - interrupts
0128 - ports
0129 - rockchip,grf
0130
0131 unevaluatedProperties: false
0132
0133 examples:
0134 - |
0135 #include <dt-bindings/clock/rk3288-cru.h>
0136 #include <dt-bindings/interrupt-controller/arm-gic.h>
0137 #include <dt-bindings/interrupt-controller/irq.h>
0138
0139 hdmi: hdmi@ff980000 {
0140 compatible = "rockchip,rk3288-dw-hdmi";
0141 reg = <0xff980000 0x20000>;
0142 reg-io-width = <4>;
0143 ddc-i2c-bus = <&i2c5>;
0144 rockchip,grf = <&grf>;
0145 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0146 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
0147 clock-names = "iahb", "isfr";
0148
0149 ports {
0150 port {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153
0154 hdmi_in_vopb: endpoint@0 {
0155 reg = <0>;
0156 remote-endpoint = <&vopb_out_hdmi>;
0157 };
0158 hdmi_in_vopl: endpoint@1 {
0159 reg = <1>;
0160 remote-endpoint = <&vopl_out_hdmi>;
0161 };
0162 };
0163 };
0164 };
0165
0166 ...
