0001 Rockchip specific extensions to the Synopsys Designware MIPI DSI
0002 ================================
0003
0004 Required properties:
0005 - #address-cells: Should be <1>.
0006 - #size-cells: Should be <0>.
0007 - compatible: one of
0008 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
0009 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
0010 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
0011 - reg: Represent the physical address range of the controller.
0012 - interrupts: Represent the controller's interrupt to the CPU(s).
0013 - clocks, clock-names: Phandles to the controller's pll reference
0014 clock(ref) when using an internal dphy and APB clock(pclk).
0015 For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
0016 are required. As described in [1].
0017 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
0018 - ports: contain a port node with endpoint definitions as defined in [2].
0019 For vopb,set the reg = <0> and set the reg = <1> for vopl.
0020 - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
0021 - video port 1 for either a panel or subsequent encoder
0022
0023 Optional properties:
0024 - phys: from general PHY binding: the phandle for the PHY device.
0025 - phy-names: Should be "dphy" if phys references an external phy.
0026 - #phy-cells: Defined when used as ISP phy, should be 0.
0027 - power-domains: a phandle to mipi dsi power domain node.
0028 - resets: list of phandle + reset specifier pairs, as described in [3].
0029 - reset-names: string reset name, must be "apb".
0030
0031 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0032 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
0033 [3] Documentation/devicetree/bindings/reset/reset.txt
0034
0035 Example:
0036 mipi_dsi: mipi@ff960000 {
0037 #address-cells = <1>;
0038 #size-cells = <0>;
0039 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
0040 reg = <0xff960000 0x4000>;
0041 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0042 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
0043 clock-names = "ref", "pclk";
0044 resets = <&cru SRST_MIPIDSI0>;
0045 reset-names = "apb";
0046 rockchip,grf = <&grf>;
0047
0048 ports {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 mipi_in: port@0 {
0053 reg = <0>;
0054 #address-cells = <1>;
0055 #size-cells = <0>;
0056
0057 mipi_in_vopb: endpoint@0 {
0058 reg = <0>;
0059 remote-endpoint = <&vopb_out_mipi>;
0060 };
0061 mipi_in_vopl: endpoint@1 {
0062 reg = <1>;
0063 remote-endpoint = <&vopl_out_mipi>;
0064 };
0065 };
0066
0067 mipi_out: port@1 {
0068 reg = <1>;
0069 #address-cells = <1>;
0070 #size-cells = <0>;
0071
0072 mipi_out_panel: endpoint {
0073 remote-endpoint = <&panel_in_mipi>;
0074 };
0075 };
0076 };
0077
0078 panel {
0079 compatible ="boe,tv080wum-nl0";
0080 reg = <0>;
0081
0082 enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
0083 pinctrl-names = "default";
0084 pinctrl-0 = <&lcd_en>;
0085 backlight = <&backlight>;
0086
0087 port {
0088 panel_in_mipi: endpoint {
0089 remote-endpoint = <&mipi_out_panel>;
0090 };
0091 };
0092 };
0093 };
