0001 Rockchip RK3399 specific extensions to the cdn Display Port
0002 ================================
0003
0004 Required properties:
0005 - compatible: must be "rockchip,rk3399-cdn-dp"
0006
0007 - reg: physical base address of the controller and length
0008
0009 - clocks: from common clock binding: handle to dp clock.
0010
0011 - clock-names: from common clock binding:
0012 Required elements: "core-clk" "pclk" "spdif" "grf"
0013
0014 - resets : a list of phandle + reset specifier pairs
0015 - reset-names : string of reset names
0016 Required elements: "apb", "core", "dptx", "spdif"
0017 - power-domains : power-domain property defined with a phandle
0018 to respective power domain.
0019 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
0020 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
0021
0022 - rockchip,grf: this soc should set GRF regs, so need get grf here.
0023
0024 - ports: contain a port nodes with endpoint definitions as defined in
0025 Documentation/devicetree/bindings/media/video-interfaces.txt.
0026 contained 2 endpoints, connecting to the output of vop.
0027
0028 - phys: from general PHY binding: the phandle for the PHY device.
0029
0030 - extcon: extcon specifier for the Power Delivery
0031
0032 - #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
0033
0034 -------------------------------------------------------------------------------
0035
0036 Example:
0037 cdn_dp: dp@fec00000 {
0038 compatible = "rockchip,rk3399-cdn-dp";
0039 reg = <0x0 0xfec00000 0x0 0x100000>;
0040 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0041 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
0042 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
0043 clock-names = "core-clk", "pclk", "spdif", "grf";
0044 assigned-clocks = <&cru SCLK_DP_CORE>;
0045 assigned-clock-rates = <100000000>;
0046 power-domains = <&power RK3399_PD_HDCP>;
0047 phys = <&tcphy0_dp>, <&tcphy1_dp>;
0048 resets = <&cru SRST_DPTX_SPDIF_REC>;
0049 reset-names = "spdif";
0050 extcon = <&fusb0>, <&fusb1>;
0051 rockchip,grf = <&grf>;
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054 #sound-dai-cells = <1>;
0055
0056 ports {
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059
0060 dp_in: port {
0061 #address-cells = <1>;
0062 #size-cells = <0>;
0063 dp_in_vopb: endpoint@0 {
0064 reg = <0>;
0065 remote-endpoint = <&vopb_out_dp>;
0066 };
0067
0068 dp_in_vopl: endpoint@1 {
0069 reg = <1>;
0070 remote-endpoint = <&vopl_out_dp>;
0071 };
0072 };
0073 };
0074 };
