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0001 Rockchip RK3288 specific extensions to the Analogix Display Port
0002 ================================
0003 
0004 Required properties:
0005 - compatible: "rockchip,rk3288-dp",
0006               "rockchip,rk3399-edp";
0007 
0008 - reg: physical base address of the controller and length
0009 
0010 - clocks: from common clock binding: handle to dp clock.
0011           of memory mapped region.
0012 
0013 - clock-names: from common clock binding:
0014                Required elements: "dp" "pclk"
0015 
0016 - resets: Must contain an entry for each entry in reset-names.
0017           See ../reset/reset.txt for details.
0018 
0019 - pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
0020 - pinctrl-0: pin-control mode. should be <&edp_hpd>
0021 
0022 - reset-names: Must include the name "dp"
0023 
0024 - rockchip,grf: this soc should set GRF regs, so need get grf here.
0025 
0026 - ports: there are 2 port nodes with endpoint definitions as defined in
0027   Documentation/devicetree/bindings/media/video-interfaces.txt.
0028     Port 0: contained 2 endpoints, connecting to the output of vop.
0029     Port 1: contained 1 endpoint, connecting to the input of panel.
0030 
0031 Optional property for different chips:
0032 - clocks: from common clock binding: handle to grf_vio clock.
0033 
0034 - clock-names: from common clock binding:
0035                Required elements: "grf"
0036 
0037 For the below properties, please refer to Analogix DP binding document:
0038  * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
0039 - phys (required)
0040 - phy-names (required)
0041 - hpd-gpios (optional)
0042 - force-hpd (optional)
0043 -------------------------------------------------------------------------------
0044 
0045 Example:
0046         dp-controller: dp@ff970000 {
0047                 compatible = "rockchip,rk3288-dp";
0048                 reg = <0xff970000 0x4000>;
0049                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0050                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
0051                 clock-names = "dp", "pclk";
0052                 phys = <&dp_phy>;
0053                 phy-names = "dp";
0054 
0055                 rockchip,grf = <&grf>;
0056                 resets = <&cru 111>;
0057                 reset-names = "dp";
0058 
0059                 pinctrl-names = "default";
0060                 pinctrl-0 = <&edp_hpd>;
0061 
0062 
0063                 ports {
0064                         #address-cells = <1>;
0065                         #size-cells = <0>;
0066                         edp_in: port@0 {
0067                                 reg = <0>;
0068                                 #address-cells = <1>;
0069                                 #size-cells = <0>;
0070                                 edp_in_vopb: endpoint@0 {
0071                                         reg = <0>;
0072                                         remote-endpoint = <&vopb_out_edp>;
0073                                 };
0074                                 edp_in_vopl: endpoint@1 {
0075                                         reg = <1>;
0076                                         remote-endpoint = <&vopl_out_edp>;
0077                                 };
0078                         };
0079 
0080                         edp_out: port@1 {
0081                                 reg = <1>;
0082                                 #address-cells = <1>;
0083                                 #size-cells = <0>;
0084                                 edp_out_panel: endpoint {
0085                                         reg = <0>;
0086                                         remote-endpoint = <&panel_in_edp>
0087                                 };
0088                         };
0089                 };
0090         };
0091 
0092         pinctrl {
0093                 edp {
0094                         edp_hpd: edp-hpd {
0095                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
0096                         };
0097                 };
0098         };