0001 Qualcomm adreno/snapdragon MDP5 display controller
0002
0003 Description:
0004
0005 This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
0006 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
0007 controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
0008
0009 MDSS:
0010 Required properties:
0011 - compatible:
0012 * "qcom,mdss" - MDSS
0013 - reg: Physical base address and length of the controller's registers.
0014 - reg-names: The names of register regions. The following regions are required:
0015 * "mdss_phys"
0016 * "vbif_phys"
0017 - interrupts: The interrupt signal from MDSS.
0018 - interrupt-controller: identifies the node as an interrupt controller.
0019 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
0020 source, should be 1.
0021 - power-domains: a power domain consumer specifier according to
0022 Documentation/devicetree/bindings/power/power_domain.txt
0023 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
0024 - clock-names: the following clocks are required.
0025 * "iface"
0026 * "bus"
0027 * "vsync"
0028 - #address-cells: number of address cells for the MDSS children. Should be 1.
0029 - #size-cells: Should be 1.
0030 - ranges: parent bus address space is the same as the child bus address space.
0031
0032 Optional properties:
0033 - clock-names: the following clocks are optional:
0034 * "lut"
0035
0036 MDP5:
0037 Required properties:
0038 - compatible:
0039 * "qcom,mdp5" - MDP5
0040 - reg: Physical base address and length of the controller's registers.
0041 - reg-names: The names of register regions. The following regions are required:
0042 * "mdp_phys"
0043 - interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
0044 - clocks: device clocks. See ../clocks/clock-bindings.txt for details.
0045 - clock-names: the following clocks are required.
0046 - * "bus"
0047 - * "iface"
0048 - * "core"
0049 - * "vsync"
0050 - ports: contains the list of output ports from MDP. These connect to interfaces
0051 that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
0052 special case since it is a part of the MDP block itself).
0053
0054 Each output port contains an endpoint that describes how it is connected to an
0055 external interface. These are described by the standard properties documented
0056 here:
0057 Documentation/devicetree/bindings/graph.txt
0058 Documentation/devicetree/bindings/media/video-interfaces.txt
0059
0060 The availability of output ports can vary across SoC revisions:
0061
0062 For MSM8974 and APQ8084:
0063 Port 0 -> MDP_INTF0 (eDP)
0064 Port 1 -> MDP_INTF1 (DSI1)
0065 Port 2 -> MDP_INTF2 (DSI2)
0066 Port 3 -> MDP_INTF3 (HDMI)
0067
0068 For MSM8916:
0069 Port 0 -> MDP_INTF1 (DSI1)
0070
0071 For MSM8994 and MSM8996:
0072 Port 0 -> MDP_INTF1 (DSI1)
0073 Port 1 -> MDP_INTF2 (DSI2)
0074 Port 2 -> MDP_INTF3 (HDMI)
0075
0076 Optional properties:
0077 - clock-names: the following clocks are optional:
0078 * "lut"
0079 * "tbu"
0080 * "tbu_rt"
0081
0082 Example:
0083
0084 / {
0085 ...
0086
0087 mdss: mdss@1a00000 {
0088 compatible = "qcom,mdss";
0089 reg = <0x1a00000 0x1000>,
0090 <0x1ac8000 0x3000>;
0091 reg-names = "mdss_phys", "vbif_phys";
0092
0093 power-domains = <&gcc MDSS_GDSC>;
0094
0095 clocks = <&gcc GCC_MDSS_AHB_CLK>,
0096 <&gcc GCC_MDSS_AXI_CLK>,
0097 <&gcc GCC_MDSS_VSYNC_CLK>;
0098 clock-names = "iface",
0099 "bus",
0100 "vsync"
0101
0102 interrupts = <0 72 0>;
0103
0104 interrupt-controller;
0105 #interrupt-cells = <1>;
0106
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges;
0110
0111 mdp: mdp@1a01000 {
0112 compatible = "qcom,mdp5";
0113 reg = <0x1a01000 0x90000>;
0114 reg-names = "mdp_phys";
0115
0116 interrupt-parent = <&mdss>;
0117 interrupts = <0 0>;
0118
0119 clocks = <&gcc GCC_MDSS_AHB_CLK>,
0120 <&gcc GCC_MDSS_AXI_CLK>,
0121 <&gcc GCC_MDSS_MDP_CLK>,
0122 <&gcc GCC_MDSS_VSYNC_CLK>;
0123 clock-names = "iface",
0124 "bus",
0125 "core",
0126 "vsync";
0127
0128 ports {
0129 #address-cells = <1>;
0130 #size-cells = <0>;
0131
0132 port@0 {
0133 reg = <0>;
0134 mdp5_intf1_out: endpoint {
0135 remote-endpoint = <&dsi0_in>;
0136 };
0137 };
0138 };
0139 };
0140
0141 dsi0: dsi@1a98000 {
0142 ...
0143 ports {
0144 ...
0145 port@0 {
0146 reg = <0>;
0147 dsi0_in: endpoint {
0148 remote-endpoint = <&mdp5_intf1_out>;
0149 };
0150 };
0151 ...
0152 };
0153 ...
0154 };
0155
0156 dsi_phy0: dsi-phy@1a98300 {
0157 ...
0158 };
0159 };
0160 };
