display/msm/mdp4.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Qualcomm Adreno/Snapdragon MDP4 display controller
0008
0009 description: >
0010   MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
0011
0012 maintainers:
0013   - Rob Clark <robdclark@gmail.com>
0014
0015 properties:
0016   compatible:
0017     const: qcom,mdp4
0018
0019   clocks:
0020     minItems: 6
0021     maxItems: 6
0022
0023   clock-names:
0024     items:
0025       - const: core_clk
0026       - const: iface_clk
0027       - const: bus_clk
0028       - const: lut_clk
0029       - const: hdmi_clk
0030       - const: tv_clk
0031
0032   reg:
0033     maxItems: 1
0034
0035   interrupts:
0036     maxItems: 1
0037
0038   iommus:
0039     maxItems: 1
0040
0041   ports:
0042     $ref: /schemas/graph.yaml#/properties/ports
0043     properties:
0044       port@0:
0045         $ref: /schemas/graph.yaml#/properties/port
0046         description: LCDC/LVDS
0047
0048       port@1:
0049         $ref: /schemas/graph.yaml#/properties/port
0050         description: DSI1 Cmd / Video
0051
0052       port@2:
0053         $ref: /schemas/graph.yaml#/properties/port
0054         description: DSI2 Cmd / Video
0055
0056       port@3:
0057         $ref: /schemas/graph.yaml#/properties/port
0058         description: Digital TV
0059
0060   qcom,lcdc-align-lsb:
0061     type: boolean
0062     description: >
0063       Indication that LSB alignment should be used for LCDC.
0064       This is only valid for 18bpp panels.
0065
0066 required:
0067   - compatible
0068   - reg
0069   - clocks
0070   - ports
0071
0072 additionalProperties: false
0073
0074 examples:
0075   - |
0076     mdp: mdp@5100000 {
0077         compatible = "qcom,mdp4";
0078         reg = <0x05100000 0xf0000>;
0079         interrupts = <0 75 0>;
0080         clock-names =
0081             "core_clk",
0082             "iface_clk",
0083             "bus_clk",
0084             "lut_clk",
0085             "hdmi_clk",
0086             "tv_clk";
0087         clocks =
0088             <&mmcc 77>,
0089             <&mmcc 86>,
0090             <&mmcc 102>,
0091             <&mmcc 75>,
0092             <&mmcc 97>,
0093             <&mmcc 12>;
0094
0095         ports {
0096             #address-cells = <1>;
0097             #size-cells = <0>;
0098
0099             port@0 {
0100                 reg = <0>;
0101                 mdp_lvds_out: endpoint {
0102                 };
0103             };
0104
0105             port@1 {
0106                 reg = <1>;
0107                 mdp_dsi1_out: endpoint {
0108                 };
0109             };
0110
0111             port@2 {
0112                 reg = <2>;
0113                 mdp_dsi2_out: endpoint {
0114                 };
0115             };
0116
0117             port@3 {
0118                 reg = <3>;
0119                 mdp_dtv_out: endpoint {
0120                     remote-endpoint = <&hdmi_in>;
0121                 };
0122             };
0123         };
0124     };