0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004
0005 $id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Devicetree bindings for the Adreno or Snapdragon GPUs
0009
0010 maintainers:
0011 - Rob Clark <robdclark@gmail.com>
0012
0013 properties:
0014 compatible:
0015 oneOf:
0016 - description: |
0017 The driver is parsing the compat string for Adreno to
0018 figure out the gpu-id and patch level.
0019 items:
0020 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
0021 - const: qcom,adreno
0022 - description: |
0023 The driver is parsing the compat string for Imageon to
0024 figure out the gpu-id and patch level.
0025 items:
0026 - pattern: '^amd,imageon-200\.[0-1]$'
0027 - const: amd,imageon
0028
0029 clocks: true
0030
0031 clock-names: true
0032
0033 reg:
0034 minItems: 1
0035 maxItems: 3
0036
0037 reg-names:
0038 minItems: 1
0039 items:
0040 - const: kgsl_3d0_reg_memory
0041 - const: cx_mem
0042 - const: cx_dbgc
0043
0044 interrupts:
0045 maxItems: 1
0046
0047 interrupt-names:
0048 maxItems: 1
0049
0050 interconnects:
0051 minItems: 1
0052 maxItems: 2
0053
0054 interconnect-names:
0055 minItems: 1
0056 items:
0057 - const: gfx-mem
0058 - const: ocmem
0059
0060 iommus:
0061 maxItems: 1
0062
0063 sram:
0064 $ref: /schemas/types.yaml#/definitions/phandle-array
0065 minItems: 1
0066 maxItems: 4
0067 items:
0068 maxItems: 1
0069 description: |
0070 phandles to one or more reserved on-chip SRAM regions.
0071 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
0072 a4xx Snapdragon SoCs. See
0073 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
0074
0075 operating-points-v2: true
0076 opp-table:
0077 type: object
0078
0079 power-domains:
0080 maxItems: 1
0081
0082 zap-shader:
0083 type: object
0084 description: |
0085 For a5xx and a6xx devices this node contains a memory-region that
0086 points to reserved memory to store the zap shader that can be used to
0087 help bring the GPU out of secure mode.
0088 properties:
0089 memory-region:
0090 $ref: /schemas/types.yaml#/definitions/phandle
0091
0092 firmware-name:
0093 description: |
0094 Default name of the firmware to load to the remote processor.
0095
0096 "#cooling-cells":
0097 const: 2
0098
0099 nvmem-cell-names:
0100 maxItems: 1
0101
0102 nvmem-cells:
0103 description: efuse registers
0104 maxItems: 1
0105
0106 qcom,gmu:
0107 $ref: /schemas/types.yaml#/definitions/phandle
0108 description: |
0109 For GMU attached devices a phandle to the GMU device that will
0110 control the power for the GPU.
0111
0112
0113 required:
0114 - compatible
0115 - reg
0116 - interrupts
0117
0118 additionalProperties: false
0119
0120 allOf:
0121 - if:
0122 properties:
0123 compatible:
0124 contains:
0125 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
0126
0127 then:
0128 properties:
0129 clocks:
0130 minItems: 2
0131 maxItems: 7
0132
0133 clock-names:
0134 items:
0135 anyOf:
0136 - const: core
0137 description: GPU Core clock
0138 - const: iface
0139 description: GPU Interface clock
0140 - const: mem
0141 description: GPU Memory clock
0142 - const: mem_iface
0143 description: GPU Memory Interface clock
0144 - const: alt_mem_iface
0145 description: GPU Alternative Memory Interface clock
0146 - const: gfx3d
0147 description: GPU 3D engine clock
0148 - const: rbbmtimer
0149 description: GPU RBBM Timer for Adreno 5xx series
0150 minItems: 2
0151 maxItems: 7
0152
0153 required:
0154 - clocks
0155 - clock-names
0156 - if:
0157 properties:
0158 compatible:
0159 contains:
0160 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
0161
0162 then: # Since Adreno 6xx series clocks should be defined in GMU
0163 properties:
0164 clocks: false
0165 clock-names: false
0166
0167 examples:
0168 - |
0169
0170 // Example a3xx/4xx:
0171
0172 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
0173 #include <dt-bindings/clock/qcom,rpmcc.h>
0174 #include <dt-bindings/interrupt-controller/irq.h>
0175 #include <dt-bindings/interrupt-controller/arm-gic.h>
0176
0177 gpu: gpu@fdb00000 {
0178 compatible = "qcom,adreno-330.2", "qcom,adreno";
0179
0180 reg = <0xfdb00000 0x10000>;
0181 reg-names = "kgsl_3d0_reg_memory";
0182
0183 clock-names = "core", "iface", "mem_iface";
0184 clocks = <&mmcc OXILI_GFX3D_CLK>,
0185 <&mmcc OXILICX_AHB_CLK>,
0186 <&mmcc OXILICX_AXI_CLK>;
0187
0188 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0189 interrupt-names = "kgsl_3d0_irq";
0190
0191 sram = <&gpu_sram>;
0192 power-domains = <&mmcc OXILICX_GDSC>;
0193 operating-points-v2 = <&gpu_opp_table>;
0194 iommus = <&gpu_iommu 0>;
0195 #cooling-cells = <2>;
0196 };
0197
0198 ocmem@fdd00000 {
0199 compatible = "qcom,msm8974-ocmem";
0200
0201 reg = <0xfdd00000 0x2000>,
0202 <0xfec00000 0x180000>;
0203 reg-names = "ctrl", "mem";
0204
0205 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
0206 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
0207 clock-names = "core", "iface";
0208
0209 #address-cells = <1>;
0210 #size-cells = <1>;
0211 ranges = <0 0xfec00000 0x100000>;
0212
0213 gpu_sram: gpu-sram@0 {
0214 reg = <0x0 0x100000>;
0215 };
0216 };
0217 - |
0218
0219 // Example a6xx (with GMU):
0220
0221 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
0222 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0223 #include <dt-bindings/power/qcom-rpmpd.h>
0224 #include <dt-bindings/interrupt-controller/irq.h>
0225 #include <dt-bindings/interrupt-controller/arm-gic.h>
0226 #include <dt-bindings/interconnect/qcom,sdm845.h>
0227
0228 reserved-memory {
0229 #address-cells = <2>;
0230 #size-cells = <2>;
0231
0232 zap_shader_region: gpu@8f200000 {
0233 compatible = "shared-dma-pool";
0234 reg = <0x0 0x90b00000 0x0 0xa00000>;
0235 no-map;
0236 };
0237 };
0238
0239 gpu@5000000 {
0240 compatible = "qcom,adreno-630.2", "qcom,adreno";
0241
0242 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
0243 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
0244
0245 #cooling-cells = <2>;
0246
0247 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
0248
0249 iommus = <&adreno_smmu 0>;
0250
0251 operating-points-v2 = <&gpu_opp_table>;
0252
0253 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
0254 interconnect-names = "gfx-mem";
0255
0256 qcom,gmu = <&gmu>;
0257
0258 gpu_opp_table: opp-table {
0259 compatible = "operating-points-v2";
0260
0261 opp-430000000 {
0262 opp-hz = /bits/ 64 <430000000>;
0263 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
0264 opp-peak-kBps = <5412000>;
0265 };
0266
0267 opp-355000000 {
0268 opp-hz = /bits/ 64 <355000000>;
0269 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
0270 opp-peak-kBps = <3072000>;
0271 };
0272
0273 opp-267000000 {
0274 opp-hz = /bits/ 64 <267000000>;
0275 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
0276 opp-peak-kBps = <3072000>;
0277 };
0278
0279 opp-180000000 {
0280 opp-hz = /bits/ 64 <180000000>;
0281 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
0282 opp-peak-kBps = <1804000>;
0283 };
0284 };
0285
0286 zap-shader {
0287 memory-region = <&zap_shader_region>;
0288 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
0289 };
0290 };
