display/msm/gmu.yaml

0001 # SPDX-License-Identifier: GPL-2.0-only
0002 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
0003 %YAML 1.2
0004 ---
0005
0006 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
0007 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0008
0009 title: Devicetree bindings for the GMU attached to certain Adreno GPUs
0010
0011 maintainers:
0012   - Rob Clark <robdclark@gmail.com>
0013
0014 description: |
0015   These bindings describe the Graphics Management Unit (GMU) that is attached
0016   to members of the Adreno A6xx GPU family. The GMU provides on-device power
0017   management and support to improve power efficiency and reduce the load on
0018   the CPU.
0019
0020 properties:
0021   compatible:
0022     items:
0023       - enum:
0024           - qcom,adreno-gmu-630.2
0025       - const: qcom,adreno-gmu
0026
0027   reg:
0028     items:
0029       - description: Core GMU registers
0030       - description: GMU PDC registers
0031       - description: GMU PDC sequence registers
0032
0033   reg-names:
0034     items:
0035       - const: gmu
0036       - const: gmu_pdc
0037       - const: gmu_pdc_seq
0038
0039   clocks:
0040     items:
0041       - description: GMU clock
0042       - description: GPU CX clock
0043       - description: GPU AXI clock
0044       - description: GPU MEMNOC clock
0045
0046   clock-names:
0047     items:
0048       - const: gmu
0049       - const: cxo
0050       - const: axi
0051       - const: memnoc
0052
0053   interrupts:
0054     items:
0055       - description: GMU HFI interrupt
0056       - description: GMU interrupt
0057
0058
0059   interrupt-names:
0060     items:
0061       - const: hfi
0062       - const: gmu
0063
0064   power-domains:
0065     items:
0066       - description: CX power domain
0067       - description: GX power domain
0068
0069   power-domain-names:
0070     items:
0071       - const: cx
0072       - const: gx
0073
0074   iommus:
0075     maxItems: 1
0076
0077   operating-points-v2: true
0078
0079 required:
0080   - compatible
0081   - reg
0082   - reg-names
0083   - clocks
0084   - clock-names
0085   - interrupts
0086   - interrupt-names
0087   - power-domains
0088   - power-domain-names
0089   - iommus
0090   - operating-points-v2
0091
0092 additionalProperties: false
0093
0094 examples:
0095   - |
0096     #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
0097     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0098     #include <dt-bindings/interrupt-controller/irq.h>
0099     #include <dt-bindings/interrupt-controller/arm-gic.h>
0100
0101     gmu: gmu@506a000 {
0102         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
0103
0104         reg = <0x506a000 0x30000>,
0105               <0xb280000 0x10000>,
0106               <0xb480000 0x10000>;
0107         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
0108
0109         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
0110                  <&gpucc GPU_CC_CXO_CLK>,
0111                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
0112                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
0113         clock-names = "gmu", "cxo", "axi", "memnoc";
0114
0115         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
0116                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
0117         interrupt-names = "hfi", "gmu";
0118
0119         power-domains = <&gpucc GPU_CX_GDSC>,
0120                         <&gpucc GPU_GX_GDSC>;
0121         power-domain-names = "cx", "gx";
0122
0123         iommus = <&adreno_smmu 5>;
0124         operating-points-v2 = <&gmu_opp_table>;
0125     };