0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI 7nm PHY
0008
0009 maintainers:
0010 - Jonathan Marek <jonathan@marek.ca>
0011
0012 allOf:
0013 - $ref: dsi-phy-common.yaml#
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - qcom,dsi-phy-7nm
0019 - qcom,dsi-phy-7nm-8150
0020 - qcom,sc7280-dsi-phy-7nm
0021
0022 reg:
0023 items:
0024 - description: dsi phy register set
0025 - description: dsi phy lane register set
0026 - description: dsi pll register set
0027
0028 reg-names:
0029 items:
0030 - const: dsi_phy
0031 - const: dsi_phy_lane
0032 - const: dsi_pll
0033
0034 vdds-supply:
0035 description: |
0036 Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
0037
0038 phy-type:
0039 description: D-PHY (default) or C-PHY mode
0040 enum: [ 10, 11 ]
0041 default: 10
0042
0043 required:
0044 - compatible
0045 - reg
0046 - reg-names
0047 - vdds-supply
0048
0049 unevaluatedProperties: false
0050
0051 examples:
0052 - |
0053 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
0054 #include <dt-bindings/clock/qcom,rpmh.h>
0055
0056 dsi-phy@ae94400 {
0057 compatible = "qcom,dsi-phy-7nm";
0058 reg = <0x0ae94400 0x200>,
0059 <0x0ae94600 0x280>,
0060 <0x0ae94900 0x260>;
0061 reg-names = "dsi_phy",
0062 "dsi_phy_lane",
0063 "dsi_pll";
0064
0065 #clock-cells = <1>;
0066 #phy-cells = <0>;
0067
0068 vdds-supply = <&vreg_l5a_0p88>;
0069 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0070 <&rpmhcc RPMH_CXO_CLK>;
0071 clock-names = "iface", "ref";
0072 };
