0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI 28nm PHY
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 allOf:
0013 - $ref: dsi-phy-common.yaml#
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - qcom,dsi-phy-28nm-hpm
0019 - qcom,dsi-phy-28nm-lp
0020 - qcom,dsi-phy-28nm-8960
0021
0022 reg:
0023 items:
0024 - description: dsi pll register set
0025 - description: dsi phy register set
0026 - description: dsi phy regulator register set
0027
0028 reg-names:
0029 items:
0030 - const: dsi_pll
0031 - const: dsi_phy
0032 - const: dsi_phy_regulator
0033
0034 vddio-supply:
0035 description: Phandle to vdd-io regulator device node.
0036
0037 required:
0038 - compatible
0039 - reg
0040 - reg-names
0041 - vddio-supply
0042
0043 unevaluatedProperties: false
0044
0045 examples:
0046 - |
0047 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0048 #include <dt-bindings/clock/qcom,rpmh.h>
0049
0050 dsi-phy@fd922a00 {
0051 compatible = "qcom,dsi-phy-28nm-lp";
0052 reg = <0xfd922a00 0xd4>,
0053 <0xfd922b00 0x2b0>,
0054 <0xfd922d80 0x7b>;
0055 reg-names = "dsi_pll",
0056 "dsi_phy",
0057 "dsi_phy_regulator";
0058
0059 #clock-cells = <1>;
0060 #phy-cells = <0>;
0061
0062 vddio-supply = <&vddio_reg>;
0063
0064 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0065 <&rpmhcc RPMH_CXO_CLK>;
0066 clock-names = "iface", "ref";
0067 };
0068 ...
