0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI 20nm PHY
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 allOf:
0013 - $ref: dsi-phy-common.yaml#
0014
0015 properties:
0016 compatible:
0017 const: qcom,dsi-phy-20nm
0018
0019 reg:
0020 items:
0021 - description: dsi pll register set
0022 - description: dsi phy register set
0023 - description: dsi phy regulator register set
0024
0025 reg-names:
0026 items:
0027 - const: dsi_pll
0028 - const: dsi_phy
0029 - const: dsi_phy_regulator
0030
0031 vcca-supply:
0032 description: Phandle to vcca regulator device node.
0033
0034 vddio-supply:
0035 description: Phandle to vdd-io regulator device node.
0036
0037 required:
0038 - compatible
0039 - reg
0040 - reg-names
0041 - vddio-supply
0042 - vcca-supply
0043
0044 unevaluatedProperties: false
0045
0046 examples:
0047 - |
0048 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0049 #include <dt-bindings/clock/qcom,rpmh.h>
0050
0051 dsi-phy@fd922a00 {
0052 compatible = "qcom,dsi-phy-20nm";
0053 reg = <0xfd922a00 0xd4>,
0054 <0xfd922b00 0x2b0>,
0055 <0xfd922d80 0x7b>;
0056 reg-names = "dsi_pll",
0057 "dsi_phy",
0058 "dsi_phy_regulator";
0059
0060 #clock-cells = <1>;
0061 #phy-cells = <0>;
0062
0063 vcca-supply = <&vcca_reg>;
0064 vddio-supply = <&vddio_reg>;
0065
0066 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0067 <&rpmhcc RPMH_CXO_CLK>;
0068 clock-names = "iface", "ref";
0069 };
0070 ...
