0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI 14nm PHY
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 allOf:
0013 - $ref: dsi-phy-common.yaml#
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - qcom,dsi-phy-14nm
0019 - qcom,dsi-phy-14nm-660
0020 - qcom,dsi-phy-14nm-8953
0021
0022 reg:
0023 items:
0024 - description: dsi phy register set
0025 - description: dsi phy lane register set
0026 - description: dsi pll register set
0027
0028 reg-names:
0029 items:
0030 - const: dsi_phy
0031 - const: dsi_phy_lane
0032 - const: dsi_pll
0033
0034 vcca-supply:
0035 description: Phandle to vcca regulator device node.
0036
0037 required:
0038 - compatible
0039 - reg
0040 - reg-names
0041 - vcca-supply
0042
0043 unevaluatedProperties: false
0044
0045 examples:
0046 - |
0047 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0048 #include <dt-bindings/clock/qcom,rpmh.h>
0049
0050 dsi-phy@ae94400 {
0051 compatible = "qcom,dsi-phy-14nm";
0052 reg = <0x0ae94400 0x200>,
0053 <0x0ae94600 0x280>,
0054 <0x0ae94a00 0x1e0>;
0055 reg-names = "dsi_phy",
0056 "dsi_phy_lane",
0057 "dsi_pll";
0058
0059 #clock-cells = <1>;
0060 #phy-cells = <0>;
0061
0062 vcca-supply = <&vcca_reg>;
0063 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0064 <&rpmhcc RPMH_CXO_CLK>;
0065 clock-names = "iface", "ref";
0066 };
0067 ...
