0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI 10nm PHY
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 allOf:
0013 - $ref: dsi-phy-common.yaml#
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - qcom,dsi-phy-10nm
0019 - qcom,dsi-phy-10nm-8998
0020
0021 reg:
0022 items:
0023 - description: dsi phy register set
0024 - description: dsi phy lane register set
0025 - description: dsi pll register set
0026
0027 reg-names:
0028 items:
0029 - const: dsi_phy
0030 - const: dsi_phy_lane
0031 - const: dsi_pll
0032
0033 vdds-supply:
0034 description: |
0035 Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
0036 connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
0037
0038 qcom,phy-rescode-offset-top:
0039 $ref: /schemas/types.yaml#/definitions/int8-array
0040 minItems: 5
0041 maxItems: 5
0042 description:
0043 Integer array of offset for pull-up legs rescode for all five lanes.
0044 To offset the drive strength from the calibrated value in an increasing
0045 manner, -32 is the weakest and +31 is the strongest.
0046 items:
0047 minimum: -32
0048 maximum: 31
0049
0050 qcom,phy-rescode-offset-bot:
0051 $ref: /schemas/types.yaml#/definitions/int8-array
0052 minItems: 5
0053 maxItems: 5
0054 description:
0055 Integer array of offset for pull-down legs rescode for all five lanes.
0056 To offset the drive strength from the calibrated value in a decreasing
0057 manner, -32 is the weakest and +31 is the strongest.
0058 items:
0059 minimum: -32
0060 maximum: 31
0061
0062 qcom,phy-drive-ldo-level:
0063 $ref: "/schemas/types.yaml#/definitions/uint32"
0064 description:
0065 The PHY LDO has an amplitude tuning feature to adjust the LDO output
0066 for the HSTX drive. Use supported levels (mV) to offset the drive level
0067 from the default value.
0068 enum: [ 375, 400, 425, 450, 475, 500 ]
0069
0070 required:
0071 - compatible
0072 - reg
0073 - reg-names
0074 - vdds-supply
0075
0076 unevaluatedProperties: false
0077
0078 examples:
0079 - |
0080 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0081 #include <dt-bindings/clock/qcom,rpmh.h>
0082
0083 dsi-phy@ae94400 {
0084 compatible = "qcom,dsi-phy-10nm";
0085 reg = <0x0ae94400 0x200>,
0086 <0x0ae94600 0x280>,
0087 <0x0ae94a00 0x1e0>;
0088 reg-names = "dsi_phy",
0089 "dsi_phy_lane",
0090 "dsi_pll";
0091
0092 #clock-cells = <1>;
0093 #phy-cells = <0>;
0094
0095 vdds-supply = <&vdda_mipi_dsi0_pll>;
0096 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0097 <&rpmhcc RPMH_CXO_CLK>;
0098 clock-names = "iface", "ref";
0099
0100 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
0101 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
0102 qcom,phy-drive-ldo-level = <400>;
0103 };
0104 ...
