0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DSI controller
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 allOf:
0013 - $ref: "../dsi-controller.yaml#"
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - qcom,mdss-dsi-ctrl
0019 - qcom,dsi-ctrl-6g-qcm2290
0020
0021 reg:
0022 maxItems: 1
0023
0024 reg-names:
0025 const: dsi_ctrl
0026
0027 interrupts:
0028 maxItems: 1
0029
0030 clocks:
0031 items:
0032 - description: Display byte clock
0033 - description: Display byte interface clock
0034 - description: Display pixel clock
0035 - description: Display escape clock
0036 - description: Display AHB clock
0037 - description: Display AXI clock
0038
0039 clock-names:
0040 items:
0041 - const: byte
0042 - const: byte_intf
0043 - const: pixel
0044 - const: core
0045 - const: iface
0046 - const: bus
0047
0048 phys:
0049 maxItems: 1
0050
0051 phy-names:
0052 const: dsi
0053
0054 "#address-cells": true
0055
0056 "#size-cells": true
0057
0058 syscon-sfpb:
0059 description: A phandle to mmss_sfpb syscon node (only for DSIv2).
0060 $ref: "/schemas/types.yaml#/definitions/phandle"
0061
0062 qcom,dual-dsi-mode:
0063 type: boolean
0064 description: |
0065 Indicates if the DSI controller is driving a panel which needs
0066 2 DSI links.
0067
0068 assigned-clocks:
0069 minItems: 2
0070 maxItems: 2
0071 description: |
0072 Parents of "byte" and "pixel" for the given platform.
0073
0074 assigned-clock-parents:
0075 minItems: 2
0076 maxItems: 2
0077 description: |
0078 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
0079
0080 power-domains:
0081 maxItems: 1
0082
0083 operating-points-v2: true
0084
0085 ports:
0086 $ref: "/schemas/graph.yaml#/properties/ports"
0087 description: |
0088 Contains DSI controller input and output ports as children, each
0089 containing one endpoint subnode.
0090
0091 properties:
0092 port@0:
0093 $ref: "/schemas/graph.yaml#/$defs/port-base"
0094 unevaluatedProperties: false
0095 description: |
0096 Input endpoints of the controller.
0097 properties:
0098 endpoint:
0099 $ref: /schemas/media/video-interfaces.yaml#
0100 unevaluatedProperties: false
0101 properties:
0102 data-lanes:
0103 maxItems: 4
0104 minItems: 4
0105 items:
0106 enum: [ 0, 1, 2, 3 ]
0107
0108 port@1:
0109 $ref: "/schemas/graph.yaml#/$defs/port-base"
0110 unevaluatedProperties: false
0111 description: |
0112 Output endpoints of the controller.
0113 properties:
0114 endpoint:
0115 $ref: /schemas/media/video-interfaces.yaml#
0116 unevaluatedProperties: false
0117 properties:
0118 data-lanes:
0119 maxItems: 4
0120 minItems: 4
0121 items:
0122 enum: [ 0, 1, 2, 3 ]
0123
0124 required:
0125 - port@0
0126 - port@1
0127
0128 required:
0129 - compatible
0130 - reg
0131 - reg-names
0132 - interrupts
0133 - clocks
0134 - clock-names
0135 - phys
0136 - phy-names
0137 - assigned-clocks
0138 - assigned-clock-parents
0139 - power-domains
0140 - operating-points-v2
0141 - ports
0142
0143 additionalProperties: false
0144
0145 examples:
0146 - |
0147 #include <dt-bindings/interrupt-controller/arm-gic.h>
0148 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0149 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0150 #include <dt-bindings/power/qcom-rpmpd.h>
0151
0152 dsi@ae94000 {
0153 compatible = "qcom,mdss-dsi-ctrl";
0154 reg = <0x0ae94000 0x400>;
0155 reg-names = "dsi_ctrl";
0156
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159
0160 interrupt-parent = <&mdss>;
0161 interrupts = <4>;
0162
0163 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
0164 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
0165 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
0166 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
0167 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0168 <&dispcc DISP_CC_MDSS_AXI_CLK>;
0169 clock-names = "byte",
0170 "byte_intf",
0171 "pixel",
0172 "core",
0173 "iface",
0174 "bus";
0175
0176 phys = <&dsi0_phy>;
0177 phy-names = "dsi";
0178
0179 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
0180 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
0181
0182 power-domains = <&rpmhpd SC7180_CX>;
0183 operating-points-v2 = <&dsi_opp_table>;
0184
0185 ports {
0186 #address-cells = <1>;
0187 #size-cells = <0>;
0188
0189 port@0 {
0190 reg = <0>;
0191 dsi0_in: endpoint {
0192 remote-endpoint = <&dpu_intf1_out>;
0193 };
0194 };
0195
0196 port@1 {
0197 reg = <1>;
0198 dsi0_out: endpoint {
0199 remote-endpoint = <&sn65dsi86_in>;
0200 data-lanes = <0 1 2 3>;
0201 };
0202 };
0203 };
0204 };
0205 ...
