0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DPU dt properties for SDM845 target
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 description: |
0013 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
0014 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
0015 bindings of MDSS and DPU are mentioned for SDM845 target.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: qcom,sdm845-mdss
0021
0022 reg:
0023 maxItems: 1
0024
0025 reg-names:
0026 const: mdss
0027
0028 power-domains:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: Display AHB clock from gcc
0034 - description: Display core clock
0035
0036 clock-names:
0037 items:
0038 - const: iface
0039 - const: core
0040
0041 interrupts:
0042 maxItems: 1
0043
0044 interrupt-controller: true
0045
0046 "#address-cells": true
0047
0048 "#size-cells": true
0049
0050 "#interrupt-cells":
0051 const: 1
0052
0053 iommus:
0054 items:
0055 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
0056 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
0057
0058 ranges: true
0059
0060 resets:
0061 items:
0062 - description: MDSS_CORE reset
0063
0064 patternProperties:
0065 "^display-controller@[0-9a-f]+$":
0066 type: object
0067 description: Node containing the properties of DPU.
0068
0069 properties:
0070 compatible:
0071 items:
0072 - const: qcom,sdm845-dpu
0073
0074 reg:
0075 items:
0076 - description: Address offset and size for mdp register set
0077 - description: Address offset and size for vbif register set
0078
0079 reg-names:
0080 items:
0081 - const: mdp
0082 - const: vbif
0083
0084 clocks:
0085 items:
0086 - description: Display ahb clock
0087 - description: Display axi clock
0088 - description: Display core clock
0089 - description: Display vsync clock
0090
0091 clock-names:
0092 items:
0093 - const: iface
0094 - const: bus
0095 - const: core
0096 - const: vsync
0097
0098 interrupts:
0099 maxItems: 1
0100
0101 power-domains:
0102 maxItems: 1
0103
0104 operating-points-v2: true
0105 ports:
0106 $ref: /schemas/graph.yaml#/properties/ports
0107 description: |
0108 Contains the list of output ports from DPU device. These ports
0109 connect to interfaces that are external to the DPU hardware,
0110 such as DSI, DP etc. Each output port contains an endpoint that
0111 describes how it is connected to an external interface.
0112
0113 properties:
0114 port@0:
0115 $ref: /schemas/graph.yaml#/properties/port
0116 description: DPU_INTF1 (DSI1)
0117
0118 port@1:
0119 $ref: /schemas/graph.yaml#/properties/port
0120 description: DPU_INTF2 (DSI2)
0121
0122 required:
0123 - port@0
0124 - port@1
0125
0126 required:
0127 - compatible
0128 - reg
0129 - reg-names
0130 - clocks
0131 - interrupts
0132 - power-domains
0133 - operating-points-v2
0134 - ports
0135
0136 required:
0137 - compatible
0138 - reg
0139 - reg-names
0140 - power-domains
0141 - clocks
0142 - interrupts
0143 - interrupt-controller
0144 - iommus
0145 - ranges
0146
0147 additionalProperties: false
0148
0149 examples:
0150 - |
0151 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
0152 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0153 #include <dt-bindings/interrupt-controller/arm-gic.h>
0154 #include <dt-bindings/power/qcom-rpmpd.h>
0155
0156 display-subsystem@ae00000 {
0157 #address-cells = <1>;
0158 #size-cells = <1>;
0159 compatible = "qcom,sdm845-mdss";
0160 reg = <0x0ae00000 0x1000>;
0161 reg-names = "mdss";
0162 power-domains = <&dispcc MDSS_GDSC>;
0163
0164 clocks = <&gcc GCC_DISP_AHB_CLK>,
0165 <&dispcc DISP_CC_MDSS_MDP_CLK>;
0166 clock-names = "iface", "core";
0167
0168 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0169 interrupt-controller;
0170 #interrupt-cells = <1>;
0171
0172 iommus = <&apps_smmu 0x880 0x8>,
0173 <&apps_smmu 0xc80 0x8>;
0174 ranges;
0175
0176 display-controller@ae01000 {
0177 compatible = "qcom,sdm845-dpu";
0178 reg = <0x0ae01000 0x8f000>,
0179 <0x0aeb0000 0x2008>;
0180 reg-names = "mdp", "vbif";
0181
0182 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0183 <&dispcc DISP_CC_MDSS_AXI_CLK>,
0184 <&dispcc DISP_CC_MDSS_MDP_CLK>,
0185 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
0186 clock-names = "iface", "bus", "core", "vsync";
0187
0188 interrupt-parent = <&mdss>;
0189 interrupts = <0>;
0190 power-domains = <&rpmhpd SDM845_CX>;
0191 operating-points-v2 = <&mdp_opp_table>;
0192
0193 ports {
0194 #address-cells = <1>;
0195 #size-cells = <0>;
0196
0197 port@0 {
0198 reg = <0>;
0199 dpu_intf1_out: endpoint {
0200 remote-endpoint = <&dsi0_in>;
0201 };
0202 };
0203
0204 port@1 {
0205 reg = <1>;
0206 dpu_intf2_out: endpoint {
0207 remote-endpoint = <&dsi1_in>;
0208 };
0209 };
0210 };
0211 };
0212 };
0213 ...
