0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DPU dt properties for SC7280
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 description: |
0013 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
0014 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
0015 bindings of MDSS and DPU are mentioned for SC7280.
0016
0017 properties:
0018 compatible:
0019 const: qcom,sc7280-mdss
0020
0021 reg:
0022 maxItems: 1
0023
0024 reg-names:
0025 const: mdss
0026
0027 power-domains:
0028 maxItems: 1
0029
0030 clocks:
0031 items:
0032 - description: Display AHB clock from gcc
0033 - description: Display AHB clock from dispcc
0034 - description: Display core clock
0035
0036 clock-names:
0037 items:
0038 - const: iface
0039 - const: ahb
0040 - const: core
0041
0042 interrupts:
0043 maxItems: 1
0044
0045 interrupt-controller: true
0046
0047 "#address-cells": true
0048
0049 "#size-cells": true
0050
0051 "#interrupt-cells":
0052 const: 1
0053
0054 iommus:
0055 items:
0056 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
0057
0058 ranges: true
0059
0060 interconnects:
0061 items:
0062 - description: Interconnect path specifying the port ids for data bus
0063
0064 interconnect-names:
0065 const: mdp0-mem
0066
0067 resets:
0068 items:
0069 - description: MDSS_CORE reset
0070
0071 patternProperties:
0072 "^display-controller@[0-9a-f]+$":
0073 type: object
0074 description: Node containing the properties of DPU.
0075
0076 properties:
0077 compatible:
0078 const: qcom,sc7280-dpu
0079
0080 reg:
0081 items:
0082 - description: Address offset and size for mdp register set
0083 - description: Address offset and size for vbif register set
0084
0085 reg-names:
0086 items:
0087 - const: mdp
0088 - const: vbif
0089
0090 clocks:
0091 items:
0092 - description: Display hf axi clock
0093 - description: Display sf axi clock
0094 - description: Display ahb clock
0095 - description: Display lut clock
0096 - description: Display core clock
0097 - description: Display vsync clock
0098
0099 clock-names:
0100 items:
0101 - const: bus
0102 - const: nrt_bus
0103 - const: iface
0104 - const: lut
0105 - const: core
0106 - const: vsync
0107
0108 interrupts:
0109 maxItems: 1
0110
0111 power-domains:
0112 maxItems: 1
0113
0114 operating-points-v2: true
0115
0116 ports:
0117 $ref: /schemas/graph.yaml#/properties/ports
0118 description: |
0119 Contains the list of output ports from DPU device. These ports
0120 connect to interfaces that are external to the DPU hardware,
0121 such as DSI, DP etc. Each output port contains an endpoint that
0122 describes how it is connected to an external interface.
0123
0124 properties:
0125 port@0:
0126 $ref: /schemas/graph.yaml#/properties/port
0127 description: DPU_INTF1 (DSI)
0128
0129 port@1:
0130 $ref: /schemas/graph.yaml#/properties/port
0131 description: DPU_INTF5 (EDP)
0132
0133 required:
0134 - port@0
0135
0136 required:
0137 - compatible
0138 - reg
0139 - reg-names
0140 - clocks
0141 - interrupts
0142 - power-domains
0143 - operating-points-v2
0144 - ports
0145
0146 required:
0147 - compatible
0148 - reg
0149 - reg-names
0150 - power-domains
0151 - clocks
0152 - interrupts
0153 - interrupt-controller
0154 - iommus
0155 - ranges
0156
0157 additionalProperties: false
0158
0159 examples:
0160 - |
0161 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
0162 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
0163 #include <dt-bindings/interrupt-controller/arm-gic.h>
0164 #include <dt-bindings/interconnect/qcom,sc7280.h>
0165 #include <dt-bindings/power/qcom-rpmpd.h>
0166
0167 display-subsystem@ae00000 {
0168 #address-cells = <1>;
0169 #size-cells = <1>;
0170 compatible = "qcom,sc7280-mdss";
0171 reg = <0xae00000 0x1000>;
0172 reg-names = "mdss";
0173 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
0174 clocks = <&gcc GCC_DISP_AHB_CLK>,
0175 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0176 <&dispcc DISP_CC_MDSS_MDP_CLK>;
0177 clock-names = "iface",
0178 "ahb",
0179 "core";
0180
0181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0182 interrupt-controller;
0183 #interrupt-cells = <1>;
0184
0185 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
0186 interconnect-names = "mdp0-mem";
0187
0188 iommus = <&apps_smmu 0x900 0x402>;
0189 ranges;
0190
0191 display-controller@ae01000 {
0192 compatible = "qcom,sc7280-dpu";
0193 reg = <0x0ae01000 0x8f000>,
0194 <0x0aeb0000 0x2008>;
0195
0196 reg-names = "mdp", "vbif";
0197
0198 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
0199 <&gcc GCC_DISP_SF_AXI_CLK>,
0200 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0201 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
0202 <&dispcc DISP_CC_MDSS_MDP_CLK>,
0203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
0204 clock-names = "bus",
0205 "nrt_bus",
0206 "iface",
0207 "lut",
0208 "core",
0209 "vsync";
0210
0211 interrupt-parent = <&mdss>;
0212 interrupts = <0>;
0213 power-domains = <&rpmhpd SC7280_CX>;
0214 operating-points-v2 = <&mdp_opp_table>;
0215
0216 ports {
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219
0220 port@0 {
0221 reg = <0>;
0222 dpu_intf1_out: endpoint {
0223 remote-endpoint = <&dsi0_in>;
0224 };
0225 };
0226
0227 port@1 {
0228 reg = <1>;
0229 dpu_intf5_out: endpoint {
0230 remote-endpoint = <&edp_in>;
0231 };
0232 };
0233 };
0234 };
0235 };
0236 ...
