0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DPU dt properties for SC7180 target
0008
0009 maintainers:
0010 - Krishna Manikandan <quic_mkrishn@quicinc.com>
0011
0012 description: |
0013 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
0014 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
0015 bindings of MDSS and DPU are mentioned for SC7180 target.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: qcom,sc7180-mdss
0021
0022 reg:
0023 maxItems: 1
0024
0025 reg-names:
0026 const: mdss
0027
0028 power-domains:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: Display AHB clock from gcc
0034 - description: Display AHB clock from dispcc
0035 - description: Display core clock
0036
0037 clock-names:
0038 items:
0039 - const: iface
0040 - const: ahb
0041 - const: core
0042
0043 interrupts:
0044 maxItems: 1
0045
0046 interrupt-controller: true
0047
0048 "#address-cells": true
0049
0050 "#size-cells": true
0051
0052 "#interrupt-cells":
0053 const: 1
0054
0055 iommus:
0056 items:
0057 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
0058
0059 ranges: true
0060
0061 interconnects:
0062 items:
0063 - description: Interconnect path specifying the port ids for data bus
0064
0065 interconnect-names:
0066 const: mdp0-mem
0067
0068 resets:
0069 items:
0070 - description: MDSS_CORE reset
0071
0072 patternProperties:
0073 "^display-controller@[0-9a-f]+$":
0074 type: object
0075 description: Node containing the properties of DPU.
0076
0077 properties:
0078 compatible:
0079 items:
0080 - const: qcom,sc7180-dpu
0081
0082 reg:
0083 items:
0084 - description: Address offset and size for mdp register set
0085 - description: Address offset and size for vbif register set
0086
0087 reg-names:
0088 items:
0089 - const: mdp
0090 - const: vbif
0091
0092 clocks:
0093 items:
0094 - description: Display hf axi clock
0095 - description: Display ahb clock
0096 - description: Display rotator clock
0097 - description: Display lut clock
0098 - description: Display core clock
0099 - description: Display vsync clock
0100
0101 clock-names:
0102 items:
0103 - const: bus
0104 - const: iface
0105 - const: rot
0106 - const: lut
0107 - const: core
0108 - const: vsync
0109
0110 interrupts:
0111 maxItems: 1
0112
0113 power-domains:
0114 maxItems: 1
0115
0116 operating-points-v2: true
0117
0118 ports:
0119 $ref: /schemas/graph.yaml#/properties/ports
0120 description: |
0121 Contains the list of output ports from DPU device. These ports
0122 connect to interfaces that are external to the DPU hardware,
0123 such as DSI, DP etc. Each output port contains an endpoint that
0124 describes how it is connected to an external interface.
0125
0126 properties:
0127 port@0:
0128 $ref: /schemas/graph.yaml#/properties/port
0129 description: DPU_INTF1 (DSI1)
0130
0131 port@2:
0132 $ref: /schemas/graph.yaml#/properties/port
0133 description: DPU_INTF0 (DP)
0134
0135 required:
0136 - port@0
0137
0138 required:
0139 - compatible
0140 - reg
0141 - reg-names
0142 - clocks
0143 - interrupts
0144 - power-domains
0145 - operating-points-v2
0146 - ports
0147
0148 required:
0149 - compatible
0150 - reg
0151 - reg-names
0152 - power-domains
0153 - clocks
0154 - interrupts
0155 - interrupt-controller
0156 - iommus
0157 - ranges
0158
0159 additionalProperties: false
0160
0161 examples:
0162 - |
0163 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
0164 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
0165 #include <dt-bindings/interrupt-controller/arm-gic.h>
0166 #include <dt-bindings/interconnect/qcom,sdm845.h>
0167 #include <dt-bindings/power/qcom-rpmpd.h>
0168
0169 display-subsystem@ae00000 {
0170 #address-cells = <1>;
0171 #size-cells = <1>;
0172 compatible = "qcom,sc7180-mdss";
0173 reg = <0xae00000 0x1000>;
0174 reg-names = "mdss";
0175 power-domains = <&dispcc MDSS_GDSC>;
0176 clocks = <&gcc GCC_DISP_AHB_CLK>,
0177 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0178 <&dispcc DISP_CC_MDSS_MDP_CLK>;
0179 clock-names = "iface", "ahb", "core";
0180
0181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0182 interrupt-controller;
0183 #interrupt-cells = <1>;
0184
0185 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
0186 interconnect-names = "mdp0-mem";
0187
0188 iommus = <&apps_smmu 0x800 0x2>;
0189 ranges;
0190
0191 display-controller@ae01000 {
0192 compatible = "qcom,sc7180-dpu";
0193 reg = <0x0ae01000 0x8f000>,
0194 <0x0aeb0000 0x2008>;
0195
0196 reg-names = "mdp", "vbif";
0197
0198 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
0199 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0200 <&dispcc DISP_CC_MDSS_ROT_CLK>,
0201 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
0202 <&dispcc DISP_CC_MDSS_MDP_CLK>,
0203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
0204 clock-names = "bus", "iface", "rot", "lut", "core",
0205 "vsync";
0206
0207 interrupt-parent = <&mdss>;
0208 interrupts = <0>;
0209 power-domains = <&rpmhpd SC7180_CX>;
0210 operating-points-v2 = <&mdp_opp_table>;
0211
0212 ports {
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215
0216 port@0 {
0217 reg = <0>;
0218 dpu_intf1_out: endpoint {
0219 remote-endpoint = <&dsi0_in>;
0220 };
0221 };
0222
0223 port@2 {
0224 reg = <2>;
0225 dpu_intf0_out: endpoint {
0226 remote-endpoint = <&dp_in>;
0227 };
0228 };
0229 };
0230 };
0231 };
0232 ...
