0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DPU dt properties for QCM2290 target
0008
0009 maintainers:
0010 - Loic Poulain <loic.poulain@linaro.org>
0011
0012 description: |
0013 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
0014 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
0015 and DPU are mentioned for QCM2290 target.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: qcom,qcm2290-mdss
0021
0022 reg:
0023 maxItems: 1
0024
0025 reg-names:
0026 const: mdss
0027
0028 power-domains:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: Display AHB clock from gcc
0034 - description: Display AXI clock
0035 - description: Display core clock
0036
0037 clock-names:
0038 items:
0039 - const: iface
0040 - const: bus
0041 - const: core
0042
0043 interrupts:
0044 maxItems: 1
0045
0046 interrupt-controller: true
0047
0048 "#address-cells": true
0049
0050 "#size-cells": true
0051
0052 "#interrupt-cells":
0053 const: 1
0054
0055 iommus:
0056 items:
0057 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
0058 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
0059
0060 ranges: true
0061
0062 interconnects:
0063 items:
0064 - description: Interconnect path specifying the port ids for data bus
0065
0066 interconnect-names:
0067 const: mdp0-mem
0068
0069 resets:
0070 items:
0071 - description: MDSS_CORE reset
0072
0073 patternProperties:
0074 "^display-controller@[0-9a-f]+$":
0075 type: object
0076 description: Node containing the properties of DPU.
0077
0078 properties:
0079 compatible:
0080 items:
0081 - const: qcom,qcm2290-dpu
0082
0083 reg:
0084 items:
0085 - description: Address offset and size for mdp register set
0086 - description: Address offset and size for vbif register set
0087
0088 reg-names:
0089 items:
0090 - const: mdp
0091 - const: vbif
0092
0093 clocks:
0094 items:
0095 - description: Display AXI clock from gcc
0096 - description: Display AHB clock from dispcc
0097 - description: Display core clock from dispcc
0098 - description: Display lut clock from dispcc
0099 - description: Display vsync clock from dispcc
0100
0101 clock-names:
0102 items:
0103 - const: bus
0104 - const: iface
0105 - const: core
0106 - const: lut
0107 - const: vsync
0108
0109 interrupts:
0110 maxItems: 1
0111
0112 power-domains:
0113 maxItems: 1
0114
0115 operating-points-v2: true
0116
0117 ports:
0118 $ref: /schemas/graph.yaml#/properties/ports
0119 description: |
0120 Contains the list of output ports from DPU device. These ports
0121 connect to interfaces that are external to the DPU hardware,
0122 such as DSI. Each output port contains an endpoint that
0123 describes how it is connected to an external interface.
0124
0125 properties:
0126 port@0:
0127 $ref: /schemas/graph.yaml#/properties/port
0128 description: DPU_INTF1 (DSI1)
0129
0130 required:
0131 - port@0
0132
0133 required:
0134 - compatible
0135 - reg
0136 - reg-names
0137 - clocks
0138 - interrupts
0139 - power-domains
0140 - operating-points-v2
0141 - ports
0142
0143 required:
0144 - compatible
0145 - reg
0146 - reg-names
0147 - power-domains
0148 - clocks
0149 - interrupts
0150 - interrupt-controller
0151 - iommus
0152 - ranges
0153
0154 additionalProperties: false
0155
0156 examples:
0157 - |
0158 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
0159 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
0160 #include <dt-bindings/interrupt-controller/arm-gic.h>
0161 #include <dt-bindings/interconnect/qcom,qcm2290.h>
0162 #include <dt-bindings/power/qcom-rpmpd.h>
0163
0164 mdss: mdss@5e00000 {
0165 #address-cells = <1>;
0166 #size-cells = <1>;
0167 compatible = "qcom,qcm2290-mdss";
0168 reg = <0x05e00000 0x1000>;
0169 reg-names = "mdss";
0170 power-domains = <&dispcc MDSS_GDSC>;
0171 clocks = <&gcc GCC_DISP_AHB_CLK>,
0172 <&gcc GCC_DISP_HF_AXI_CLK>,
0173 <&dispcc DISP_CC_MDSS_MDP_CLK>;
0174 clock-names = "iface", "bus", "core";
0175
0176 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0177 interrupt-controller;
0178 #interrupt-cells = <1>;
0179
0180 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
0181 interconnect-names = "mdp0-mem";
0182
0183 iommus = <&apps_smmu 0x420 0x2>,
0184 <&apps_smmu 0x421 0x0>;
0185 ranges;
0186
0187 mdss_mdp: display-controller@5e01000 {
0188 compatible = "qcom,qcm2290-dpu";
0189 reg = <0x05e01000 0x8f000>,
0190 <0x05eb0000 0x2008>;
0191 reg-names = "mdp", "vbif";
0192
0193 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
0194 <&dispcc DISP_CC_MDSS_AHB_CLK>,
0195 <&dispcc DISP_CC_MDSS_MDP_CLK>,
0196 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
0197 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
0198 clock-names = "bus", "iface", "core", "lut", "vsync";
0199
0200 operating-points-v2 = <&mdp_opp_table>;
0201 power-domains = <&rpmpd QCM2290_VDDCX>;
0202
0203 interrupt-parent = <&mdss>;
0204 interrupts = <0>;
0205
0206 ports {
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209
0210 port@0 {
0211 reg = <0>;
0212 dpu_intf1_out: endpoint {
0213 remote-endpoint = <&dsi0_in>;
0214 };
0215 };
0216 };
0217 };
0218 };
0219 ...
