0001 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display DPU dt properties for MSM8998 target
0008
0009 maintainers:
0010 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
0011
0012 description: |
0013 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
0014 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
0015 bindings of MDSS and DPU are mentioned for MSM8998 target.
0016
0017 properties:
0018 compatible:
0019 items:
0020 - const: qcom,msm8998-mdss
0021
0022 reg:
0023 maxItems: 1
0024
0025 reg-names:
0026 const: mdss
0027
0028 power-domains:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: Display AHB clock
0034 - description: Display AXI clock
0035 - description: Display core clock
0036
0037 clock-names:
0038 items:
0039 - const: iface
0040 - const: bus
0041 - const: core
0042
0043 interrupts:
0044 maxItems: 1
0045
0046 interrupt-controller: true
0047
0048 "#address-cells": true
0049
0050 "#size-cells": true
0051
0052 "#interrupt-cells":
0053 const: 1
0054
0055 iommus:
0056 items:
0057 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
0058
0059 ranges: true
0060
0061 patternProperties:
0062 "^display-controller@[0-9a-f]+$":
0063 type: object
0064 description: Node containing the properties of DPU.
0065
0066 properties:
0067 compatible:
0068 items:
0069 - const: qcom,msm8998-dpu
0070
0071 reg:
0072 items:
0073 - description: Address offset and size for mdp register set
0074 - description: Address offset and size for regdma register set
0075 - description: Address offset and size for vbif register set
0076 - description: Address offset and size for non-realtime vbif register set
0077
0078 reg-names:
0079 items:
0080 - const: mdp
0081 - const: regdma
0082 - const: vbif
0083 - const: vbif_nrt
0084
0085 clocks:
0086 items:
0087 - description: Display ahb clock
0088 - description: Display axi clock
0089 - description: Display mem-noc clock
0090 - description: Display core clock
0091 - description: Display vsync clock
0092
0093 clock-names:
0094 items:
0095 - const: iface
0096 - const: bus
0097 - const: mnoc
0098 - const: core
0099 - const: vsync
0100
0101 interrupts:
0102 maxItems: 1
0103
0104 power-domains:
0105 maxItems: 1
0106
0107 operating-points-v2: true
0108 ports:
0109 $ref: /schemas/graph.yaml#/properties/ports
0110 description: |
0111 Contains the list of output ports from DPU device. These ports
0112 connect to interfaces that are external to the DPU hardware,
0113 such as DSI, DP etc. Each output port contains an endpoint that
0114 describes how it is connected to an external interface.
0115
0116 properties:
0117 port@0:
0118 $ref: /schemas/graph.yaml#/properties/port
0119 description: DPU_INTF1 (DSI1)
0120
0121 port@1:
0122 $ref: /schemas/graph.yaml#/properties/port
0123 description: DPU_INTF2 (DSI2)
0124
0125 required:
0126 - port@0
0127 - port@1
0128
0129 required:
0130 - compatible
0131 - reg
0132 - reg-names
0133 - clocks
0134 - interrupts
0135 - power-domains
0136 - operating-points-v2
0137 - ports
0138
0139 required:
0140 - compatible
0141 - reg
0142 - reg-names
0143 - power-domains
0144 - clocks
0145 - interrupts
0146 - interrupt-controller
0147 - iommus
0148 - ranges
0149
0150 additionalProperties: false
0151
0152 examples:
0153 - |
0154 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
0155 #include <dt-bindings/interrupt-controller/arm-gic.h>
0156 #include <dt-bindings/power/qcom-rpmpd.h>
0157
0158 mdss: display-subsystem@c900000 {
0159 compatible = "qcom,msm8998-mdss";
0160 reg = <0x0c900000 0x1000>;
0161 reg-names = "mdss";
0162
0163 clocks = <&mmcc MDSS_AHB_CLK>,
0164 <&mmcc MDSS_AXI_CLK>,
0165 <&mmcc MDSS_MDP_CLK>;
0166 clock-names = "iface", "bus", "core";
0167
0168 #address-cells = <1>;
0169 #interrupt-cells = <1>;
0170 #size-cells = <1>;
0171
0172 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0173 interrupt-controller;
0174 iommus = <&mmss_smmu 0>;
0175
0176 power-domains = <&mmcc MDSS_GDSC>;
0177 ranges;
0178
0179 display-controller@c901000 {
0180 compatible = "qcom,msm8998-dpu";
0181 reg = <0x0c901000 0x8f000>,
0182 <0x0c9a8e00 0xf0>,
0183 <0x0c9b0000 0x2008>,
0184 <0x0c9b8000 0x1040>;
0185 reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
0186
0187 clocks = <&mmcc MDSS_AHB_CLK>,
0188 <&mmcc MDSS_AXI_CLK>,
0189 <&mmcc MNOC_AHB_CLK>,
0190 <&mmcc MDSS_MDP_CLK>,
0191 <&mmcc MDSS_VSYNC_CLK>;
0192 clock-names = "iface", "bus", "mnoc", "core", "vsync";
0193
0194 interrupt-parent = <&mdss>;
0195 interrupts = <0>;
0196 operating-points-v2 = <&mdp_opp_table>;
0197 power-domains = <&rpmpd MSM8998_VDDMX>;
0198
0199 ports {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202
0203 port@0 {
0204 reg = <0>;
0205 dpu_intf1_out: endpoint {
0206 remote-endpoint = <&dsi0_in>;
0207 };
0208 };
0209
0210 port@1 {
0211 reg = <1>;
0212 dpu_intf2_out: endpoint {
0213 remote-endpoint = <&dsi1_in>;
0214 };
0215 };
0216 };
0217 };
0218 };
0219 ...
