0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MSM Display Port Controller
0008
0009 maintainers:
0010 - Kuogee Hsieh <quic_khsieh@quicinc.com>
0011
0012 description: |
0013 Device tree bindings for DisplayPort host controller for MSM targets
0014 that are compatible with VESA DisplayPort interface specification.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - qcom,sc7180-dp
0020 - qcom,sc7280-dp
0021 - qcom,sc7280-edp
0022 - qcom,sc8180x-dp
0023 - qcom,sc8180x-edp
0024 - qcom,sm8350-dp
0025
0026 reg:
0027 items:
0028 - description: ahb register block
0029 - description: aux register block
0030 - description: link register block
0031 - description: p0 register block
0032 - description: p1 register block
0033
0034 interrupts:
0035 maxItems: 1
0036
0037 clocks:
0038 items:
0039 - description: AHB clock to enable register access
0040 - description: Display Port AUX clock
0041 - description: Display Port Link clock
0042 - description: Link interface clock between DP and PHY
0043 - description: Display Port Pixel clock
0044
0045 clock-names:
0046 items:
0047 - const: core_iface
0048 - const: core_aux
0049 - const: ctrl_link
0050 - const: ctrl_link_iface
0051 - const: stream_pixel
0052
0053 assigned-clocks:
0054 items:
0055 - description: link clock source
0056 - description: pixel clock source
0057
0058 assigned-clock-parents:
0059 items:
0060 - description: phy 0 parent
0061 - description: phy 1 parent
0062
0063 phys:
0064 maxItems: 1
0065
0066 phy-names:
0067 items:
0068 - const: dp
0069
0070 operating-points-v2:
0071 maxItems: 1
0072
0073 power-domains:
0074 maxItems: 1
0075
0076 "#sound-dai-cells":
0077 const: 0
0078
0079 vdda-0p9-supply: true
0080 vdda-1p2-supply: true
0081
0082 ports:
0083 $ref: /schemas/graph.yaml#/properties/ports
0084 properties:
0085 port@0:
0086 $ref: /schemas/graph.yaml#/properties/port
0087 description: Input endpoint of the controller
0088
0089 port@1:
0090 $ref: /schemas/graph.yaml#/properties/port
0091 description: Output endpoint of the controller
0092
0093 required:
0094 - compatible
0095 - reg
0096 - interrupts
0097 - clocks
0098 - clock-names
0099 - phys
0100 - phy-names
0101 - "#sound-dai-cells"
0102 - power-domains
0103 - ports
0104
0105 additionalProperties: false
0106
0107 examples:
0108 - |
0109 #include <dt-bindings/interrupt-controller/arm-gic.h>
0110 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
0111 #include <dt-bindings/power/qcom-rpmpd.h>
0112
0113 displayport-controller@ae90000 {
0114 compatible = "qcom,sc7180-dp";
0115 reg = <0xae90000 0x200>,
0116 <0xae90200 0x200>,
0117 <0xae90400 0xc00>,
0118 <0xae91000 0x400>,
0119 <0xae91400 0x400>;
0120 interrupt-parent = <&mdss>;
0121 interrupts = <12>;
0122 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
0123 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
0124 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
0125 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
0126 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
0127 clock-names = "core_iface", "core_aux",
0128 "ctrl_link",
0129 "ctrl_link_iface", "stream_pixel";
0130
0131 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
0132 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
0133
0134 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
0135
0136 phys = <&dp_phy>;
0137 phy-names = "dp";
0138
0139 #sound-dai-cells = <0>;
0140
0141 power-domains = <&rpmhpd SC7180_CX>;
0142
0143 vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
0144 vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>;
0145
0146 ports {
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149
0150 port@0 {
0151 reg = <0>;
0152 endpoint {
0153 remote-endpoint = <&dpu_intf0_out>;
0154 };
0155 };
0156
0157 port@1 {
0158 reg = <1>;
0159 endpoint {
0160 remote-endpoint = <&typec>;
0161 };
0162 };
0163 };
0164 };
0165 ...
