0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek Write Direct Memory Access
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek Write Direct Memory Access(WDMA) component used to write
0015 the data into DMA.
0016 WDMA device node must be siblings to the central MMSYS_CONFIG node.
0017 For a description of the MMSYS_CONFIG binding, see
0018 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0019 for details.
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - items:
0025 - const: mediatek,mt8173-disp-wdma
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 power-domains:
0034 description: A phandle and PM domain specifier as defined by bindings of
0035 the power controller specified by phandle. See
0036 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0037
0038 clocks:
0039 items:
0040 - description: WDMA Clock
0041
0042 iommus:
0043 description:
0044 This property should point to the respective IOMMU block with master port as argument,
0045 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
0046
0047 mediatek,gce-client-reg:
0048 description: The register of client driver can be configured by gce with
0049 4 arguments defined in this property, such as phandle of gce, subsys id,
0050 register offset and size. Each GCE subsys id is mapping to a client
0051 defined in the header include/dt-bindings/gce/<chip>-gce.h.
0052 $ref: /schemas/types.yaml#/definitions/phandle-array
0053 maxItems: 1
0054
0055 required:
0056 - compatible
0057 - reg
0058 - interrupts
0059 - power-domains
0060 - clocks
0061 - iommus
0062
0063 additionalProperties: false
0064
0065 examples:
0066 - |
0067 #include <dt-bindings/interrupt-controller/arm-gic.h>
0068 #include <dt-bindings/clock/mt8173-clk.h>
0069 #include <dt-bindings/power/mt8173-power.h>
0070 #include <dt-bindings/gce/mt8173-gce.h>
0071 #include <dt-bindings/memory/mt8173-larb-port.h>
0072
0073 soc {
0074 #address-cells = <2>;
0075 #size-cells = <2>;
0076
0077 wdma0: wdma@14011000 {
0078 compatible = "mediatek,mt8173-disp-wdma";
0079 reg = <0 0x14011000 0 0x1000>;
0080 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
0081 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0082 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
0083 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
0084 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
0085 };
0086 };
