0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display UFOe
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek display UFOe stands for Unified Frame Optimization engine.
0015 UFOe can cut the data rate for DSI port which may lead to reduce power
0016 consumption.
0017 UFOe device node must be siblings to the central MMSYS_CONFIG node.
0018 For a description of the MMSYS_CONFIG binding, see
0019 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0020 for details.
0021
0022 properties:
0023 compatible:
0024 oneOf:
0025 - items:
0026 - const: mediatek,mt8173-disp-ufoe
0027
0028 reg:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 power-domains:
0035 description: A phandle and PM domain specifier as defined by bindings of
0036 the power controller specified by phandle. See
0037 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0038
0039 clocks:
0040 items:
0041 - description: UFOe Clock
0042
0043 required:
0044 - compatible
0045 - reg
0046 - interrupts
0047 - power-domains
0048 - clocks
0049
0050 additionalProperties: false
0051
0052 examples:
0053 - |
0054 #include <dt-bindings/interrupt-controller/arm-gic.h>
0055 #include <dt-bindings/clock/mt8173-clk.h>
0056 #include <dt-bindings/power/mt8173-power.h>
0057 soc {
0058 #address-cells = <2>;
0059 #size-cells = <2>;
0060
0061 ufoe@1401a000 {
0062 compatible = "mediatek,mt8173-disp-ufoe";
0063 reg = <0 0x1401a000 0 0x1000>;
0064 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
0065 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0066 clocks = <&mmsys CLK_MM_DISP_UFOE>;
0067 };
0068 };
