0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display split
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek display split, namely SPLIT, is used to split stream to two
0015 encoders.
0016 SPLIT device node must be siblings to the central MMSYS_CONFIG node.
0017 For a description of the MMSYS_CONFIG binding, see
0018 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0019 for details.
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - items:
0025 - const: mediatek,mt8173-disp-split
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 power-domains:
0034 description: A phandle and PM domain specifier as defined by bindings of
0035 the power controller specified by phandle. See
0036 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0037
0038 clocks:
0039 items:
0040 - description: SPLIT Clock
0041
0042 required:
0043 - compatible
0044 - reg
0045 - power-domains
0046 - clocks
0047
0048 additionalProperties: false
0049
0050 examples:
0051 - |
0052 #include <dt-bindings/clock/mt8173-clk.h>
0053 #include <dt-bindings/power/mt8173-power.h>
0054
0055 soc {
0056 #address-cells = <2>;
0057 #size-cells = <2>;
0058
0059 split0: split@14018000 {
0060 compatible = "mediatek,mt8173-disp-split";
0061 reg = <0 0x14018000 0 0x1000>;
0062 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
0063 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
0064 };
0065 };
