0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek Read Direct Memory Access
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek Read Direct Memory Access(RDMA) component used to read the
0015 data into DMA. It provides real time data to the back-end panel
0016 driver, such as DSI, DPI and DP_INTF.
0017 It contains one line buffer to store the sufficient pixel data.
0018 RDMA device node must be siblings to the central MMSYS_CONFIG node.
0019 For a description of the MMSYS_CONFIG binding, see
0020 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0021 for details.
0022
0023 properties:
0024 compatible:
0025 oneOf:
0026 - items:
0027 - const: mediatek,mt2701-disp-rdma
0028 - items:
0029 - const: mediatek,mt8173-disp-rdma
0030 - items:
0031 - const: mediatek,mt8183-disp-rdma
0032 - items:
0033 - const: mediatek,mt8195-disp-rdma
0034 - items:
0035 - enum:
0036 - mediatek,mt7623-disp-rdma
0037 - mediatek,mt2712-disp-rdma
0038 - const: mediatek,mt2701-disp-rdma
0039 - items:
0040 - enum:
0041 - mediatek,mt8186-disp-rdma
0042 - mediatek,mt8192-disp-rdma
0043 - const: mediatek,mt8183-disp-rdma
0044
0045 reg:
0046 maxItems: 1
0047
0048 interrupts:
0049 maxItems: 1
0050
0051 power-domains:
0052 description: A phandle and PM domain specifier as defined by bindings of
0053 the power controller specified by phandle. See
0054 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0055
0056 clocks:
0057 items:
0058 - description: RDMA Clock
0059
0060 iommus:
0061 description:
0062 This property should point to the respective IOMMU block with master port as argument,
0063 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
0064
0065 mediatek,rdma-fifo-size:
0066 description:
0067 rdma fifo size may be different even in same SOC, add this property to the
0068 corresponding rdma.
0069 The value below is the Max value which defined in hardware data sheet
0070 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
0071 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
0072 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
0073 $ref: /schemas/types.yaml#/definitions/uint32
0074 enum: [8192, 5120, 2048]
0075
0076 mediatek,gce-client-reg:
0077 description: The register of client driver can be configured by gce with
0078 4 arguments defined in this property, such as phandle of gce, subsys id,
0079 register offset and size. Each GCE subsys id is mapping to a client
0080 defined in the header include/dt-bindings/gce/<chip>-gce.h.
0081 $ref: /schemas/types.yaml#/definitions/phandle-array
0082 maxItems: 1
0083
0084 required:
0085 - compatible
0086 - reg
0087 - interrupts
0088 - power-domains
0089 - clocks
0090 - iommus
0091
0092 additionalProperties: false
0093
0094 examples:
0095 - |
0096 #include <dt-bindings/interrupt-controller/arm-gic.h>
0097 #include <dt-bindings/clock/mt8173-clk.h>
0098 #include <dt-bindings/power/mt8173-power.h>
0099 #include <dt-bindings/gce/mt8173-gce.h>
0100 #include <dt-bindings/memory/mt8173-larb-port.h>
0101
0102 soc {
0103 #address-cells = <2>;
0104 #size-cells = <2>;
0105
0106 rdma0: rdma@1400e000 {
0107 compatible = "mediatek,mt8173-disp-rdma";
0108 reg = <0 0x1400e000 0 0x1000>;
0109 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
0110 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0111 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
0112 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
0113 mediatek,rdma-fifo-size = <8192>;
0114 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
0115 };
0116 };
