0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display postmask
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek display postmask, namely POSTMASK, provides round corner pattern
0015 generation.
0016 POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
0017 For a description of the MMSYS_CONFIG binding, see
0018 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0019 for details.
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - items:
0025 - const: mediatek,mt8192-disp-postmask
0026 - items:
0027 - enum:
0028 - mediatek,mt8186-disp-postmask
0029 - const: mediatek,mt8192-disp-postmask
0030
0031 reg:
0032 maxItems: 1
0033
0034 interrupts:
0035 maxItems: 1
0036
0037 power-domains:
0038 description: A phandle and PM domain specifier as defined by bindings of
0039 the power controller specified by phandle. See
0040 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0041
0042 clocks:
0043 items:
0044 - description: POSTMASK Clock
0045
0046 mediatek,gce-client-reg:
0047 description: The register of client driver can be configured by gce with
0048 4 arguments defined in this property, such as phandle of gce, subsys id,
0049 register offset and size. Each GCE subsys id is mapping to a client
0050 defined in the header include/dt-bindings/gce/<chip>-gce.h.
0051 $ref: /schemas/types.yaml#/definitions/phandle-array
0052 maxItems: 1
0053
0054 required:
0055 - compatible
0056 - reg
0057 - interrupts
0058 - power-domains
0059 - clocks
0060
0061 additionalProperties: false
0062
0063 examples:
0064 - |
0065 #include <dt-bindings/interrupt-controller/arm-gic.h>
0066 #include <dt-bindings/clock/mt8192-clk.h>
0067 #include <dt-bindings/power/mt8192-power.h>
0068 #include <dt-bindings/gce/mt8192-gce.h>
0069
0070 soc {
0071 #address-cells = <2>;
0072 #size-cells = <2>;
0073
0074 postmask0: postmask@1400d000 {
0075 compatible = "mediatek,mt8192-disp-postmask";
0076 reg = <0 0x1400d000 0 0x1000>;
0077 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
0078 power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
0079 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
0080 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
0081 };
0082 };
