display/mediatek/mediatek%2Covl.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display overlay
0008
0009 maintainers:
0010   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011   - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014   Mediatek display overlay, namely OVL, can do alpha blending from
0015   the memory.
0016   OVL device node must be siblings to the central MMSYS_CONFIG node.
0017   For a description of the MMSYS_CONFIG binding, see
0018   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0019   for details.
0020
0021 properties:
0022   compatible:
0023     oneOf:
0024       - items:
0025           - const: mediatek,mt2701-disp-ovl
0026       - items:
0027           - const: mediatek,mt8173-disp-ovl
0028       - items:
0029           - const: mediatek,mt8183-disp-ovl
0030       - items:
0031           - const: mediatek,mt8192-disp-ovl
0032       - items:
0033           - enum:
0034               - mediatek,mt7623-disp-ovl
0035               - mediatek,mt2712-disp-ovl
0036           - const: mediatek,mt2701-disp-ovl
0037       - items:
0038           - enum:
0039               - mediatek,mt8195-disp-ovl
0040           - const: mediatek,mt8183-disp-ovl
0041       - items:
0042           - enum:
0043               - mediatek,mt8186-disp-ovl
0044           - const: mediatek,mt8192-disp-ovl
0045
0046   reg:
0047     maxItems: 1
0048
0049   interrupts:
0050     maxItems: 1
0051
0052   power-domains:
0053     description: A phandle and PM domain specifier as defined by bindings of
0054       the power controller specified by phandle. See
0055       Documentation/devicetree/bindings/power/power-domain.yaml for details.
0056
0057   clocks:
0058     items:
0059       - description: OVL Clock
0060
0061   iommus:
0062     description:
0063       This property should point to the respective IOMMU block with master port as argument,
0064       see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
0065
0066   mediatek,gce-client-reg:
0067     description: The register of client driver can be configured by gce with
0068       4 arguments defined in this property, such as phandle of gce, subsys id,
0069       register offset and size. Each GCE subsys id is mapping to a client
0070       defined in the header include/dt-bindings/gce/<chip>-gce.h.
0071     $ref: /schemas/types.yaml#/definitions/phandle-array
0072     maxItems: 1
0073
0074 required:
0075   - compatible
0076   - reg
0077   - interrupts
0078   - power-domains
0079   - clocks
0080   - iommus
0081
0082 additionalProperties: false
0083
0084 examples:
0085   - |
0086     #include <dt-bindings/interrupt-controller/arm-gic.h>
0087     #include <dt-bindings/clock/mt8173-clk.h>
0088     #include <dt-bindings/power/mt8173-power.h>
0089     #include <dt-bindings/gce/mt8173-gce.h>
0090     #include <dt-bindings/memory/mt8173-larb-port.h>
0091
0092     soc {
0093         #address-cells = <2>;
0094         #size-cells = <2>;
0095
0096         ovl0: ovl@1400c000 {
0097             compatible = "mediatek,mt8173-disp-ovl";
0098             reg = <0 0x1400c000 0 0x1000>;
0099             interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
0100             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0101             clocks = <&mmsys CLK_MM_DISP_OVL0>;
0102             iommus = <&iommu M4U_PORT_DISP_OVL0>;
0103             mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
0104         };
0105     };