0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display merge
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
0015 inputs into one side-by-side output.
0016 MERGE device node must be siblings to the central MMSYS_CONFIG node.
0017 For a description of the MMSYS_CONFIG binding, see
0018 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0019 for details.
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - items:
0025 - const: mediatek,mt8173-disp-merge
0026 - items:
0027 - const: mediatek,mt8195-disp-merge
0028
0029 reg:
0030 maxItems: 1
0031
0032 interrupts:
0033 maxItems: 1
0034
0035 power-domains:
0036 description: A phandle and PM domain specifier as defined by bindings of
0037 the power controller specified by phandle. See
0038 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0039
0040 clocks:
0041 minItems: 1
0042 maxItems: 2
0043
0044 clock-names:
0045 oneOf:
0046 - items:
0047 - const: merge
0048 - items:
0049 - const: merge
0050 - const: merge_async
0051
0052 mediatek,merge-fifo-en:
0053 description:
0054 The setting of merge fifo is mainly provided for the display latency
0055 buffer to ensure that the back-end panel display data will not be
0056 underrun, a little more data is needed in the fifo.
0057 According to the merge fifo settings, when the water level is detected
0058 to be insufficient, it will trigger RDMA sending ultra and preulra
0059 command to SMI to speed up the data rate.
0060 type: boolean
0061
0062 mediatek,merge-mute:
0063 description: Support mute function. Mute the content of merge output.
0064 type: boolean
0065
0066 mediatek,gce-client-reg:
0067 description: The register of client driver can be configured by gce with
0068 4 arguments defined in this property, such as phandle of gce, subsys id,
0069 register offset and size. Each GCE subsys id is mapping to a client
0070 defined in the header include/dt-bindings/gce/<chip>-gce.h.
0071 $ref: /schemas/types.yaml#/definitions/phandle-array
0072 maxItems: 1
0073
0074 resets:
0075 description: reset controller
0076 See Documentation/devicetree/bindings/reset/reset.txt for details.
0077 maxItems: 1
0078
0079 required:
0080 - compatible
0081 - reg
0082 - power-domains
0083 - clocks
0084
0085 additionalProperties: false
0086
0087 examples:
0088 - |
0089 #include <dt-bindings/interrupt-controller/arm-gic.h>
0090 #include <dt-bindings/clock/mt8173-clk.h>
0091 #include <dt-bindings/power/mt8173-power.h>
0092
0093 soc {
0094 #address-cells = <2>;
0095 #size-cells = <2>;
0096
0097 merge@14017000 {
0098 compatible = "mediatek,mt8173-disp-merge";
0099 reg = <0 0x14017000 0 0x1000>;
0100 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
0101 clocks = <&mmsys CLK_MM_DISP_MERGE>;
0102 clock-names = "merge";
0103 };
0104 };
