0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek MDP RDMA
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description:
0014 The MediaTek MDP RDMA stands for Read Direct Memory Access.
0015 It provides real time data to the back-end panel driver, such as DSI,
0016 DPI and DP_INTF.
0017 It contains one line buffer to store the sufficient pixel data.
0018 RDMA device node must be siblings to the central MMSYS_CONFIG node.
0019 For a description of the MMSYS_CONFIG binding, see
0020 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
0021
0022 properties:
0023 compatible:
0024 const: mediatek,mt8195-vdo1-rdma
0025
0026 reg:
0027 maxItems: 1
0028
0029 interrupts:
0030 maxItems: 1
0031
0032 power-domains:
0033 maxItems: 1
0034
0035 clocks:
0036 items:
0037 - description: RDMA Clock
0038
0039 iommus:
0040 maxItems: 1
0041
0042 mediatek,gce-client-reg:
0043 description:
0044 The register of display function block to be set by gce. There are 4 arguments,
0045 such as gce node, subsys id, offset and register size. The subsys id that is
0046 mapping to the register of display function blocks is defined in the gce header
0047 include/dt-bindings/gce/<chip>-gce.h of each chips.
0048 $ref: /schemas/types.yaml#/definitions/phandle-array
0049 items:
0050 items:
0051 - description: phandle of GCE
0052 - description: GCE subsys id
0053 - description: register offset
0054 - description: register size
0055 maxItems: 1
0056
0057 required:
0058 - compatible
0059 - reg
0060 - power-domains
0061 - clocks
0062 - iommus
0063 - mediatek,gce-client-reg
0064
0065 additionalProperties: false
0066
0067 examples:
0068 - |
0069 #include <dt-bindings/interrupt-controller/arm-gic.h>
0070 #include <dt-bindings/clock/mt8195-clk.h>
0071 #include <dt-bindings/power/mt8195-power.h>
0072 #include <dt-bindings/gce/mt8195-gce.h>
0073 #include <dt-bindings/memory/mt8195-memory-port.h>
0074
0075 soc {
0076 #address-cells = <2>;
0077 #size-cells = <2>;
0078
0079 rdma@1c104000 {
0080 compatible = "mediatek,mt8195-vdo1-rdma";
0081 reg = <0 0x1c104000 0 0x1000>;
0082 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
0083 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
0084 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
0085 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
0086 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
0087 };
0088 };
