0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek HDMI Encoder Device Tree Bindings
0008
0009 maintainers:
0010 - CK Hu <ck.hu@mediatek.com>
0011 - Jitao shi <jitao.shi@mediatek.com>
0012
0013 description: |
0014 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
0015 its parallel input.
0016
0017 properties:
0018 compatible:
0019 enum:
0020 - mediatek,mt2701-hdmi
0021 - mediatek,mt7623-hdmi
0022 - mediatek,mt8167-hdmi
0023 - mediatek,mt8173-hdmi
0024
0025 reg:
0026 maxItems: 1
0027
0028 interrupts:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: Pixel Clock
0034 - description: HDMI PLL
0035 - description: Bit Clock
0036 - description: S/PDIF Clock
0037
0038 clock-names:
0039 items:
0040 - const: pixel
0041 - const: pll
0042 - const: bclk
0043 - const: spdif
0044
0045 phys:
0046 maxItems: 1
0047
0048 phy-names:
0049 items:
0050 - const: hdmi
0051
0052 mediatek,syscon-hdmi:
0053 $ref: '/schemas/types.yaml#/definitions/phandle-array'
0054 items:
0055 - items:
0056 - description: phandle to system configuration registers
0057 - description: register offset in the system configuration registers
0058 description: |
0059 phandle link and register offset to the system configuration registers.
0060
0061 ports:
0062 $ref: /schemas/graph.yaml#/properties/ports
0063
0064 properties:
0065 port@0:
0066 $ref: /schemas/graph.yaml#/properties/port
0067 description: |
0068 Input port node. This port should be connected to a DPI output port.
0069
0070 port@1:
0071 $ref: /schemas/graph.yaml#/properties/port
0072 description: |
0073 Output port node. This port should be connected to the input port of a connector
0074 node that contains a ddc-i2c-bus property, or to the input port of an attached
0075 bridge chip, such as a SlimPort transmitter.
0076
0077 required:
0078 - port@0
0079 - port@1
0080
0081 required:
0082 - compatible
0083 - reg
0084 - interrupts
0085 - clocks
0086 - clock-names
0087 - phys
0088 - phy-names
0089 - mediatek,syscon-hdmi
0090 - ports
0091
0092 additionalProperties: false
0093
0094 examples:
0095 - |
0096 #include <dt-bindings/clock/mt8173-clk.h>
0097 #include <dt-bindings/interrupt-controller/arm-gic.h>
0098 #include <dt-bindings/interrupt-controller/irq.h>
0099 hdmi0: hdmi@14025000 {
0100 compatible = "mediatek,mt8173-hdmi";
0101 reg = <0x14025000 0x400>;
0102 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
0103 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
0104 <&mmsys CLK_MM_HDMI_PLLCK>,
0105 <&mmsys CLK_MM_HDMI_AUDIO>,
0106 <&mmsys CLK_MM_HDMI_SPDIF>;
0107 clock-names = "pixel", "pll", "bclk", "spdif";
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&hdmi_pin>;
0110 phys = <&hdmi_phy>;
0111 phy-names = "hdmi";
0112 mediatek,syscon-hdmi = <&mmsys 0x900>;
0113
0114 ports {
0115 #address-cells = <1>;
0116 #size-cells = <0>;
0117
0118 port@0 {
0119 reg = <0>;
0120
0121 hdmi0_in: endpoint {
0122 remote-endpoint = <&dpi0_out>;
0123 };
0124 };
0125
0126 port@1 {
0127 reg = <1>;
0128
0129 hdmi0_out: endpoint {
0130 remote-endpoint = <&hdmi_con_in>;
0131 };
0132 };
0133 };
0134 };
0135
0136 ...
