0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek DSI Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012 - Jitao Shi <jitao.shi@mediatek.com>
0013 - Xinlei Lee <xinlei.lee@mediatek.com>
0014
0015 description: |
0016 The MediaTek DSI function block is a sink of the display subsystem and can
0017 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
0018 channel output.
0019
0020 allOf:
0021 - $ref: /schemas/display/dsi-controller.yaml#
0022
0023 properties:
0024 compatible:
0025 enum:
0026 - mediatek,mt2701-dsi
0027 - mediatek,mt7623-dsi
0028 - mediatek,mt8167-dsi
0029 - mediatek,mt8173-dsi
0030 - mediatek,mt8183-dsi
0031 - mediatek,mt8186-dsi
0032
0033 reg:
0034 maxItems: 1
0035
0036 interrupts:
0037 maxItems: 1
0038
0039 power-domains:
0040 maxItems: 1
0041
0042 clocks:
0043 items:
0044 - description: Engine Clock
0045 - description: Digital Clock
0046 - description: HS Clock
0047
0048 clock-names:
0049 items:
0050 - const: engine
0051 - const: digital
0052 - const: hs
0053
0054 resets:
0055 maxItems: 1
0056
0057 phys:
0058 maxItems: 1
0059
0060 phy-names:
0061 items:
0062 - const: dphy
0063
0064 port:
0065 $ref: /schemas/graph.yaml#/properties/port
0066 description:
0067 Output port node. This port should be connected to the input
0068 port of an attached DSI panel or DSI-to-eDP encoder chip.
0069
0070 required:
0071 - compatible
0072 - reg
0073 - interrupts
0074 - power-domains
0075 - clocks
0076 - clock-names
0077 - phys
0078 - phy-names
0079 - port
0080
0081 unevaluatedProperties: false
0082
0083 examples:
0084 - |
0085 #include <dt-bindings/clock/mt8183-clk.h>
0086 #include <dt-bindings/interrupt-controller/arm-gic.h>
0087 #include <dt-bindings/interrupt-controller/irq.h>
0088 #include <dt-bindings/power/mt8183-power.h>
0089 #include <dt-bindings/phy/phy.h>
0090 #include <dt-bindings/reset/mt8183-resets.h>
0091
0092 soc {
0093 #address-cells = <2>;
0094 #size-cells = <2>;
0095
0096 dsi0: dsi@14014000 {
0097 compatible = "mediatek,mt8183-dsi";
0098 reg = <0 0x14014000 0 0x1000>;
0099 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
0100 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
0101 clocks = <&mmsys CLK_MM_DSI0_MM>,
0102 <&mmsys CLK_MM_DSI0_IF>,
0103 <&mipi_tx0>;
0104 clock-names = "engine", "digital", "hs";
0105 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
0106 phys = <&mipi_tx0>;
0107 phy-names = "dphy";
0108 port {
0109 dsi0_out: endpoint {
0110 remote-endpoint = <&panel_in>;
0111 };
0112 };
0113 };
0114 };
0115
0116 ...
