0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: mediatek display DSC controller
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 The DSC standard is a specification of the algorithms used for
0015 compressing and decompressing image display streams, including
0016 the specification of the syntax and semantics of the compressed
0017 video bit stream. DSC is designed for real-time systems with
0018 real-time compression, transmission, decompression and Display.
0019
0020 properties:
0021 compatible:
0022 oneOf:
0023 - items:
0024 - const: mediatek,mt8195-disp-dsc
0025
0026 reg:
0027 maxItems: 1
0028
0029 interrupts:
0030 maxItems: 1
0031
0032 clocks:
0033 items:
0034 - description: DSC Wrapper Clock
0035
0036 power-domains:
0037 description: A phandle and PM domain specifier as defined by bindings of
0038 the power controller specified by phandle. See
0039 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0040
0041 mediatek,gce-client-reg:
0042 description:
0043 The register of client driver can be configured by gce with 4 arguments
0044 defined in this property, such as phandle of gce, subsys id,
0045 register offset and size.
0046 Each subsys id is mapping to a base address of display function blocks
0047 register which is defined in the gce header
0048 include/dt-bindings/gce/<chip>-gce.h.
0049 $ref: /schemas/types.yaml#/definitions/phandle-array
0050 maxItems: 1
0051
0052 required:
0053 - compatible
0054 - reg
0055 - interrupts
0056 - power-domains
0057 - clocks
0058
0059 additionalProperties: false
0060
0061 examples:
0062 - |
0063 #include <dt-bindings/interrupt-controller/arm-gic.h>
0064 #include <dt-bindings/clock/mt8195-clk.h>
0065 #include <dt-bindings/power/mt8195-power.h>
0066 #include <dt-bindings/gce/mt8195-gce.h>
0067
0068 soc {
0069 #address-cells = <2>;
0070 #size-cells = <2>;
0071
0072 dsc0: disp_dsc_wrap@1c009000 {
0073 compatible = "mediatek,mt8195-disp-dsc";
0074 reg = <0 0x1c009000 0 0x1000>;
0075 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
0076 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
0077 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
0078 mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
0079 };
0080 };
