0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display dither processor
0008
0009 maintainers:
0010 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011 - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014 Mediatek display dither processor, namely DITHER, works by approximating
0015 unavailable colors with available colors and by mixing and matching available
0016 colors to mimic unavailable ones.
0017 DITHER device node must be siblings to the central MMSYS_CONFIG node.
0018 For a description of the MMSYS_CONFIG binding, see
0019 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0020 for details.
0021
0022 properties:
0023 compatible:
0024 oneOf:
0025 - items:
0026 - const: mediatek,mt8183-disp-dither
0027 - items:
0028 - enum:
0029 - mediatek,mt8186-disp-dither
0030 - mediatek,mt8192-disp-dither
0031 - mediatek,mt8195-disp-dither
0032 - const: mediatek,mt8183-disp-dither
0033
0034 reg:
0035 maxItems: 1
0036
0037 interrupts:
0038 maxItems: 1
0039
0040 power-domains:
0041 description: A phandle and PM domain specifier as defined by bindings of
0042 the power controller specified by phandle. See
0043 Documentation/devicetree/bindings/power/power-domain.yaml for details.
0044
0045 clocks:
0046 items:
0047 - description: DITHER Clock
0048
0049 mediatek,gce-client-reg:
0050 description: The register of client driver can be configured by gce with
0051 4 arguments defined in this property, such as phandle of gce, subsys id,
0052 register offset and size. Each GCE subsys id is mapping to a client
0053 defined in the header include/dt-bindings/gce/<chip>-gce.h.
0054 $ref: /schemas/types.yaml#/definitions/phandle-array
0055 maxItems: 1
0056
0057 required:
0058 - compatible
0059 - reg
0060 - interrupts
0061 - power-domains
0062 - clocks
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068 #include <dt-bindings/interrupt-controller/arm-gic.h>
0069 #include <dt-bindings/clock/mt8183-clk.h>
0070 #include <dt-bindings/power/mt8183-power.h>
0071 #include <dt-bindings/gce/mt8183-gce.h>
0072
0073 soc {
0074 #address-cells = <2>;
0075 #size-cells = <2>;
0076
0077 dither0: dither@14012000 {
0078 compatible = "mediatek,mt8183-disp-dither";
0079 reg = <0 0x14012000 0 0x1000>;
0080 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
0081 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
0082 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
0083 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
0084 };
0085 };
