display/mediatek/mediatek%2Ccolor.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek display color processor
0008
0009 maintainers:
0010   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0011   - Philipp Zabel <p.zabel@pengutronix.de>
0012
0013 description: |
0014   Mediatek display color processor, namely COLOR, provides hue, luma and
0015   saturation adjustments to get better picture quality and to have one panel
0016   resemble the other in their output characteristics.
0017   COLOR device node must be siblings to the central MMSYS_CONFIG node.
0018   For a description of the MMSYS_CONFIG binding, see
0019   Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
0020   for details.
0021
0022 properties:
0023   compatible:
0024     oneOf:
0025       - items:
0026           - const: mediatek,mt2701-disp-color
0027       - items:
0028           - const: mediatek,mt8167-disp-color
0029       - items:
0030           - const: mediatek,mt8173-disp-color
0031       - items:
0032           - enum:
0033               - mediatek,mt7623-disp-color
0034               - mediatek,mt2712-disp-color
0035           - const: mediatek,mt2701-disp-color
0036       - items:
0037           - enum:
0038               - mediatek,mt8183-disp-color
0039               - mediatek,mt8186-disp-color
0040               - mediatek,mt8192-disp-color
0041               - mediatek,mt8195-disp-color
0042           - const: mediatek,mt8173-disp-color
0043   reg:
0044     maxItems: 1
0045
0046   interrupts:
0047     maxItems: 1
0048
0049   power-domains:
0050     description: A phandle and PM domain specifier as defined by bindings of
0051       the power controller specified by phandle. See
0052       Documentation/devicetree/bindings/power/power-domain.yaml for details.
0053
0054   clocks:
0055     items:
0056       - description: COLOR Clock
0057
0058   mediatek,gce-client-reg:
0059     description: The register of client driver can be configured by gce with
0060       4 arguments defined in this property, such as phandle of gce, subsys id,
0061       register offset and size. Each GCE subsys id is mapping to a client
0062       defined in the header include/dt-bindings/gce/<chip>-gce.h.
0063     $ref: /schemas/types.yaml#/definitions/phandle-array
0064     maxItems: 1
0065
0066 required:
0067   - compatible
0068   - reg
0069   - interrupts
0070   - power-domains
0071   - clocks
0072
0073 additionalProperties: false
0074
0075 examples:
0076   - |
0077     #include <dt-bindings/interrupt-controller/arm-gic.h>
0078     #include <dt-bindings/clock/mt8173-clk.h>
0079     #include <dt-bindings/power/mt8173-power.h>
0080     #include <dt-bindings/gce/mt8173-gce.h>
0081
0082     soc {
0083         #address-cells = <2>;
0084         #size-cells = <2>;
0085
0086         color0: color@14013000 {
0087             compatible = "mediatek,mt8173-disp-color";
0088             reg = <0 0x14013000 0 0x1000>;
0089             interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
0090             power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
0091             clocks = <&mmsys CLK_MM_DISP_COLOR0>;
0092             mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
0093         };
0094     };