0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/lvds.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: LVDS Display Common Properties
0008
0009 maintainers:
0010 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
0011 - Thierry Reding <thierry.reding@gmail.com>
0012
0013 description: |+
0014 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
0015 incompatible data link layers have been used over time to transmit image data
0016 to LVDS devices. This bindings supports devices compatible with the following
0017 specifications.
0018
0019 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
0020 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
0021 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
0022 Semiconductor
0023 [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
0024 Electronics Standards Association (VESA)
0025
0026 Device compatible with those specifications have been marketed under the
0027 FPD-Link and FlatLink brands.
0028
0029 properties:
0030 data-mapping:
0031 enum:
0032 - jeida-18
0033 - jeida-24
0034 - vesa-24
0035 description: |
0036 The color signals mapping order.
0037
0038 LVDS data mappings are defined as follows.
0039
0040 - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
0041 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
0042
0043 Slot 0 1 2 3 4 5 6
0044 ________________ _________________
0045 Clock \_______________________/
0046 ______ ______ ______ ______ ______ ______ ______
0047 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
0048 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
0049 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
0050
0051 - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
0052 specifications. Data are transferred as follows on 4 LVDS lanes.
0053
0054 Slot 0 1 2 3 4 5 6
0055 ________________ _________________
0056 Clock \_______________________/
0057 ______ ______ ______ ______ ______ ______ ______
0058 DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
0059 DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
0060 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
0061 DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
0062
0063 - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
0064 Data are transferred as follows on 4 LVDS lanes.
0065
0066 Slot 0 1 2 3 4 5 6
0067 ________________ _________________
0068 Clock \_______________________/
0069 ______ ______ ______ ______ ______ ______ ______
0070 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
0071 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
0072 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
0073 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
0074
0075 Control signals are mapped as follows.
0076
0077 CTL0: HSync
0078 CTL1: VSync
0079 CTL2: Data Enable
0080 CTL3: 0
0081
0082 data-mirror:
0083 type: boolean
0084 description:
0085 If set, reverse the bit order described in the data mappings below on all
0086 data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
0087
0088 additionalProperties: true
0089
0090 ...
