0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 # Copyright 2019 NXP
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: iMX8MQ Display Controller Subsystem (DCSS)
0009
0010 maintainers:
0011 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
0012
0013 description:
0014
0015 The DCSS (display controller sub system) is used to source up to three
0016 display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
0017 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
0018 image processing capabilities are included to provide a solution capable of
0019 driving next generation high dynamic range displays.
0020
0021 properties:
0022 compatible:
0023 const: nxp,imx8mq-dcss
0024
0025 reg:
0026 items:
0027 - description: DCSS base address and size, up to IRQ steer start
0028 - description: DCSS BLKCTL base address and size
0029
0030 interrupts:
0031 items:
0032 - description: Context loader completion and error interrupt
0033 - description: DTG interrupt used to signal context loader trigger time
0034 - description: DTG interrupt for Vblank
0035
0036 interrupt-names:
0037 items:
0038 - const: ctxld
0039 - const: ctxld_kick
0040 - const: vblank
0041
0042 clocks:
0043 items:
0044 - description: Display APB clock for all peripheral PIO access interfaces
0045 - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
0046 - description: RTRAM clock
0047 - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
0048 - description: DTRC clock, needed by video decompressor
0049
0050 clock-names:
0051 items:
0052 - const: apb
0053 - const: axi
0054 - const: rtrm
0055 - const: pix
0056 - const: dtrc
0057
0058 assigned-clocks:
0059 items:
0060 - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
0061 - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
0062 - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
0063 IMX8MQ_VIDEO_PLL1_REF_SEL
0064
0065 assigned-clock-parents:
0066 items:
0067 - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
0068 - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
0069 - description: Phandle and clock specifier of IMX8MQ_CLK_27M
0070
0071 assigned-clock-rates:
0072 items:
0073 - description: Must be 800 MHz
0074 - description: Must be 400 MHz
0075
0076 port:
0077 $ref: /schemas/graph.yaml#/properties/port
0078 description:
0079 A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
0080
0081 additionalProperties: false
0082
0083 examples:
0084 - |
0085 #include <dt-bindings/clock/imx8mq-clock.h>
0086 dcss: display-controller@32e00000 {
0087 compatible = "nxp,imx8mq-dcss";
0088 reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
0089 interrupts = <6>, <8>, <9>;
0090 interrupt-names = "ctxld", "ctxld_kick", "vblank";
0091 interrupt-parent = <&irqsteer>;
0092 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
0093 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
0094 <&clk IMX8MQ_CLK_DISP_DTRC>;
0095 clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
0096 assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
0097 <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
0098 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
0099 <&clk IMX8MQ_CLK_27M>;
0100 assigned-clock-rates = <800000000>,
0101 <400000000>;
0102 port {
0103 dcss_out: endpoint {
0104 remote-endpoint = <&hdmi_in>;
0105 };
0106 };
0107 };
