0001 Device-Tree bindings for LVDS Display Bridge (ldb)
0002
0003 LVDS Display Bridge
0004 ===================
0005
0006 The LVDS Display Bridge device tree node contains up to two lvds-channel
0007 nodes describing each of the two LVDS encoder channels of the bridge.
0008
0009 Required properties:
0010 - #address-cells : should be <1>
0011 - #size-cells : should be <0>
0012 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
0013 Both LDB versions are similar, but i.MX6 has an additional
0014 multiplexer in the front to select any of the four IPU display
0015 interfaces as input for each LVDS channel.
0016 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
0017 The phandle points to the iomuxc-gpr region containing the LVDS
0018 control register.
0019 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
0020 the display interface selector clocks, as described in
0021 Documentation/devicetree/bindings/clock/clock-bindings.txt
0022 The following clocks are expected on i.MX53:
0023 "di0_pll" - LDB LVDS channel 0 mux
0024 "di1_pll" - LDB LVDS channel 1 mux
0025 "di0" - LDB LVDS channel 0 gate
0026 "di1" - LDB LVDS channel 1 gate
0027 "di0_sel" - IPU1 DI0 mux
0028 "di1_sel" - IPU1 DI1 mux
0029 On i.MX6q the following additional clocks are needed:
0030 "di2_sel" - IPU2 DI0 mux
0031 "di3_sel" - IPU2 DI1 mux
0032 The needed clock numbers for each are documented in
0033 Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
0034 Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
0035
0036 Optional properties:
0037 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
0038 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
0039 not used on i.MX6q
0040 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
0041 be configured - one input will be distributed on both outputs in dual
0042 channel mode
0043
0044 LVDS Channel
0045 ============
0046
0047 Each LVDS Channel has to contain either an of graph link to a panel device node
0048 or a display-timings node that describes the video timings for the connected
0049 LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
0050
0051 Required properties:
0052 - reg : should be <0> or <1>
0053 - port: Input and output port nodes with endpoint definitions as defined in
0054 Documentation/devicetree/bindings/graph.txt.
0055 On i.MX5, the internal two-input-multiplexer is used. Due to hardware
0056 limitations, only one input port (port@[0,1]) can be used for each channel
0057 (lvds-channel@[0,1], respectively).
0058 On i.MX6, there should be four input ports (port@[0-3]) that correspond
0059 to the four LVDS multiplexer inputs.
0060 A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
0061 to a panel input port. Optionally, the output port can be left out if
0062 display-timings are used instead.
0063
0064 Optional properties (required if display-timings are used):
0065 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
0066 - display-timings : A node that describes the display timings as defined in
0067 Documentation/devicetree/bindings/display/panel/display-timing.txt.
0068 - fsl,data-mapping : should be "spwg" or "jeida"
0069 This describes how the color bits are laid out in the
0070 serialized LVDS signal.
0071 - fsl,data-width : should be <18> or <24>
0072
0073 example:
0074
0075 gpr: iomuxc-gpr@53fa8000 {
0076 /* ... */
0077 };
0078
0079 ldb: ldb@53fa8008 {
0080 #address-cells = <1>;
0081 #size-cells = <0>;
0082 compatible = "fsl,imx53-ldb";
0083 gpr = <&gpr>;
0084 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
0085 <&clks IMX5_CLK_LDB_DI1_SEL>,
0086 <&clks IMX5_CLK_IPU_DI0_SEL>,
0087 <&clks IMX5_CLK_IPU_DI1_SEL>,
0088 <&clks IMX5_CLK_LDB_DI0_GATE>,
0089 <&clks IMX5_CLK_LDB_DI1_GATE>;
0090 clock-names = "di0_pll", "di1_pll",
0091 "di0_sel", "di1_sel",
0092 "di0", "di1";
0093
0094 /* Using an of-graph endpoint link to connect the panel */
0095 lvds-channel@0 {
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098 reg = <0>;
0099
0100 port@0 {
0101 reg = <0>;
0102
0103 lvds0_in: endpoint {
0104 remote-endpoint = <&ipu_di0_lvds0>;
0105 };
0106 };
0107
0108 port@2 {
0109 reg = <2>;
0110
0111 lvds0_out: endpoint {
0112 remote-endpoint = <&panel_in>;
0113 };
0114 };
0115 };
0116
0117 /* Using display-timings and fsl,data-mapping/width instead */
0118 lvds-channel@1 {
0119 #address-cells = <1>;
0120 #size-cells = <0>;
0121 reg = <1>;
0122 fsl,data-mapping = "spwg";
0123 fsl,data-width = <24>;
0124
0125 display-timings {
0126 /* ... */
0127 };
0128
0129 port@1 {
0130 reg = <1>;
0131
0132 lvds1_in: endpoint {
0133 remote-endpoint = <&ipu_di1_lvds1>;
0134 };
0135 };
0136 };
0137 };
0138
0139 panel: lvds-panel {
0140 /* ... */
0141
0142 port {
0143 panel_in: endpoint {
0144 remote-endpoint = <&lvds0_out>;
0145 };
0146 };
0147 };
