0001 Freescale i.MX DRM master device
0002 ================================
0003
0004 The freescale i.MX DRM master device is a virtual device needed to list all
0005 IPU or other display interface nodes that comprise the graphics subsystem.
0006
0007 Required properties:
0008 - compatible: Should be "fsl,imx-display-subsystem"
0009 - ports: Should contain a list of phandles pointing to display interface ports
0010 of IPU devices
0011
0012 example:
0013
0014 display-subsystem {
0015 compatible = "fsl,imx-display-subsystem";
0016 ports = <&ipu_di0>;
0017 };
0018
0019
0020 Freescale i.MX IPUv3
0021 ====================
0022
0023 Required properties:
0024 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
0025 - imx51
0026 - imx53
0027 - imx6q
0028 - imx6qp
0029 - reg: should be register base and length as documented in the
0030 datasheet
0031 - interrupts: Should contain sync interrupt and error interrupt,
0032 in this order.
0033 - resets: phandle pointing to the system reset controller and
0034 reset line index, see reset/fsl,imx-src.txt for details
0035 Additional required properties for fsl,imx6qp-ipu:
0036 - fsl,prg: phandle to prg node associated with this IPU instance
0037 Optional properties:
0038 - port@[0-3]: Port nodes with endpoint definitions as defined in
0039 Documentation/devicetree/bindings/media/video-interfaces.txt.
0040 Ports 0 and 1 should correspond to CSI0 and CSI1,
0041 ports 2 and 3 should correspond to DI0 and DI1, respectively.
0042
0043 example:
0044
0045 ipu: ipu@18000000 {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048 compatible = "fsl,imx53-ipu";
0049 reg = <0x18000000 0x080000000>;
0050 interrupts = <11 10>;
0051 resets = <&src 2>;
0052
0053 ipu_di0: port@2 {
0054 reg = <2>;
0055
0056 ipu_di0_disp0: endpoint {
0057 remote-endpoint = <&display_in>;
0058 };
0059 };
0060 };
0061
0062 Freescale i.MX PRE (Prefetch Resolve Engine)
0063 ============================================
0064
0065 Required properties:
0066 - compatible: should be "fsl,imx6qp-pre"
0067 - reg: should be register base and length as documented in the
0068 datasheet
0069 - clocks : phandle to the PRE axi clock input, as described
0070 in Documentation/devicetree/bindings/clock/clock-bindings.txt and
0071 Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
0072 - clock-names: should be "axi"
0073 - interrupts: should contain the PRE interrupt
0074 - fsl,iram: phandle pointing to the mmio-sram device node, that should be
0075 used for the PRE SRAM double buffer.
0076
0077 example:
0078
0079 pre@21c8000 {
0080 compatible = "fsl,imx6qp-pre";
0081 reg = <0x021c8000 0x1000>;
0082 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
0083 clocks = <&clks IMX6QDL_CLK_PRE0>;
0084 clock-names = "axi";
0085 fsl,iram = <&ocram2>;
0086 };
0087
0088 Freescale i.MX PRG (Prefetch Resolve Gasket)
0089 ============================================
0090
0091 Required properties:
0092 - compatible: should be "fsl,imx6qp-prg"
0093 - reg: should be register base and length as documented in the
0094 datasheet
0095 - clocks : phandles to the PRG ipg and axi clock inputs, as described
0096 in Documentation/devicetree/bindings/clock/clock-bindings.txt and
0097 Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
0098 - clock-names: should be "ipg" and "axi"
0099 - fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
0100 PRE as the first entry and the muxable PREs following.
0101
0102 example:
0103
0104 prg@21cc000 {
0105 compatible = "fsl,imx6qp-prg";
0106 reg = <0x021cc000 0x1000>;
0107 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
0108 <&clks IMX6QDL_CLK_PRG0_AXI>;
0109 clock-names = "ipg", "axi";
0110 fsl,pres = <&pre1>, <&pre2>, <&pre3>;
0111 };
0112
0113 Parallel display support
0114 ========================
0115
0116 Required properties:
0117 - compatible: Should be "fsl,imx-parallel-display"
0118 Optional properties:
0119 - interface-pix-fmt: How this display is connected to the
0120 display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
0121 and "lvds666".
0122 - edid: verbatim EDID data block describing attached display.
0123 - ddc: phandle describing the i2c bus handling the display data
0124 channel
0125 - port@[0-1]: Port nodes with endpoint definitions as defined in
0126 Documentation/devicetree/bindings/media/video-interfaces.txt.
0127 Port 0 is the input port connected to the IPU display interface,
0128 port 1 is the output port connected to a panel.
0129
0130 example:
0131
0132 disp0 {
0133 compatible = "fsl,imx-parallel-display";
0134 edid = [edid-data];
0135 interface-pix-fmt = "rgb24";
0136
0137 port@0 {
0138 reg = <0>;
0139
0140 display_in: endpoint {
0141 remote-endpoint = <&ipu_di0_disp0>;
0142 };
0143 };
0144
0145 port@1 {
0146 reg = <1>;
0147
0148 display_out: endpoint {
0149 remote-endpoint = <&panel_in>;
0150 };
0151 };
0152 };
0153
0154 panel {
0155 ...
0156
0157 port {
0158 panel_in: endpoint {
0159 remote-endpoint = <&display_out>;
0160 };
0161 };
0162 };
