0001 Freescale imx21 Framebuffer
0002
0003 This framebuffer driver supports devices imx1, imx21, imx25, and imx27.
0004
0005 Required properties:
0006 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
0007 - reg : Should contain 1 register ranges(address and length)
0008 - interrupts : One interrupt of the fb dev
0009
0010 Required nodes:
0011 - display: Phandle to a display node as described in
0012 Documentation/devicetree/bindings/display/panel/display-timing.txt
0013 Additional, the display node has to define properties:
0014 - bits-per-pixel: Bits per pixel
0015 - fsl,pcr: LCDC PCR value
0016 A display node may optionally define
0017 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
0018
0019 Optional properties:
0020 - lcd-supply: Regulator for LCD supply voltage.
0021 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
0022 register is not modified as recommended by the datasheet.
0023 - fsl,lpccr: Contrast Control Register value. This property provides the
0024 default value for the contrast control register.
0025 If that property is omitted, the register is zeroed.
0026 - fsl,lscr1: LCDC Sharp Configuration Register value.
0027
0028 Example:
0029
0030 imxfb: fb@10021000 {
0031 compatible = "fsl,imx21-fb";
0032 interrupts = <61>;
0033 reg = <0x10021000 0x1000>;
0034 display = <&display0>;
0035 };
0036
0037 ...
0038
0039 display0: display0 {
0040 model = "Primeview-PD050VL1";
0041 bits-per-pixel = <16>;
0042 fsl,pcr = <0xf0c88080>; /* non-standard but required */
0043 display-timings {
0044 native-mode = <&timing_disp0>;
0045 timing_disp0: 640x480 {
0046 hactive = <640>;
0047 vactive = <480>;
0048 hback-porch = <112>;
0049 hfront-porch = <36>;
0050 hsync-len = <32>;
0051 vback-porch = <33>;
0052 vfront-porch = <33>;
0053 vsync-len = <2>;
0054 clock-frequency = <25000000>;
0055 };
0056 };
0057 };
