0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm PrimeCell Color LCD Controller PL110/PL111
0008
0009 maintainers:
0010 - Liviu Dudau <Liviu.Dudau@arm.com>
0011 - Andre Przywara <andre.przywara@arm.com>
0012
0013 description:
0014 The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
0015 a framebuffer region in system memory, and creates timed signals for
0016 a variety of LCD panels.
0017
0018 # We need a select here so we don't match all nodes with 'arm,primecell'
0019 select:
0020 properties:
0021 compatible:
0022 contains:
0023 enum:
0024 - arm,pl110
0025 - arm,pl111
0026 required:
0027 - compatible
0028
0029 properties:
0030 compatible:
0031 items:
0032 - enum:
0033 - arm,pl110
0034 - arm,pl111
0035 - const: arm,primecell
0036
0037 reg:
0038 maxItems: 1
0039
0040 interrupt-names:
0041 oneOf:
0042 - const: combined
0043 description:
0044 The IP provides four individual interrupt lines, but also one
0045 combined line. If the integration only connects this line to the
0046 interrupt controller, this single interrupt is noted here.
0047 - items:
0048 - const: mbe # CLCDMBEINTR
0049 - const: vcomp # CLCDVCOMPINTR
0050 - const: lnbu # CLCDLNBUINTR
0051 - const: fuf # CLCDFUFINTR
0052
0053 interrupts:
0054 minItems: 1
0055 maxItems: 4
0056
0057 clock-names:
0058 items:
0059 - const: clcdclk
0060 - const: apb_pclk
0061
0062 clocks:
0063 items:
0064 - description: The CLCDCLK reference clock for the controller.
0065 - description: The HCLK AHB slave clock for the register access.
0066
0067 memory-region:
0068 maxItems: 1
0069 description:
0070 Phandle to a node describing memory to be used for the framebuffer.
0071 If not present, the framebuffer may be located anywhere in memory.
0072
0073 max-memory-bandwidth:
0074 $ref: /schemas/types.yaml#/definitions/uint32
0075 description:
0076 Maximum bandwidth in bytes per second that the cell's memory interface
0077 can handle.
0078 If not present, the memory interface is fast enough to handle all
0079 possible video modes.
0080
0081 port:
0082 $ref: /schemas/graph.yaml#/$defs/port-base
0083 additionalProperties: false
0084
0085 description:
0086 Output endpoint of the controller, connecting the LCD panel signals.
0087
0088 properties:
0089 endpoint:
0090 $ref: /schemas/graph.yaml#/$defs/endpoint-base
0091 unevaluatedProperties: false
0092
0093 properties:
0094 arm,pl11x,tft-r0g0b0-pads:
0095 $ref: /schemas/types.yaml#/definitions/uint32-array
0096 items:
0097 - description: index of CLD pad used for first red bit (R0)
0098 - description: index of CLD pad used for first green bit (G0)
0099 - description: index of CLD pad used for first blue bit (G0)
0100 deprecated: true
0101 description: |
0102 DEPRECATED. An array of three 32-bit values, defining the way
0103 CLD[23:0] pads are wired up.
0104 The first value contains the index of the "CLD" external pin (pad)
0105 used as R0 (first bit of the red component), the second value for
0106 green, the third value for blue.
0107 See also "LCD panel signal multiplexing details" paragraphs in the
0108 PL110/PL111 Technical Reference Manuals.
0109 This implicitly defines available color modes, for example:
0110 - PL111 TFT 4:4:4 panel:
0111 arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
0112 - PL110 TFT (1:)5:5:5 panel:
0113 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
0114 - PL111 TFT (1:)5:5:5 panel:
0115 arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
0116 - PL111 TFT 5:6:5 panel:
0117 arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
0118 - PL110 and PL111 TFT 8:8:8 panel:
0119 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
0120 - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
0121 arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
0122
0123 additionalProperties: false
0124
0125 required:
0126 - compatible
0127 - reg
0128 - clock-names
0129 - clocks
0130 - port
0131
0132 allOf:
0133 - if:
0134 properties:
0135 interrupts:
0136 minItems: 2
0137 required:
0138 - interrupts
0139 then:
0140 required:
0141 - interrupt-names
0142
0143 examples:
0144 - |
0145 clcd@10020000 {
0146 compatible = "arm,pl111", "arm,primecell";
0147 reg = <0x10020000 0x1000>;
0148 interrupt-names = "combined";
0149 interrupts = <44>;
0150 clocks = <&oscclk1>, <&oscclk2>;
0151 clock-names = "clcdclk", "apb_pclk";
0152 max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
0153
0154 port {
0155 clcd_pads: endpoint {
0156 remote-endpoint = <&clcd_panel>;
0157 };
0158 };
0159 };
0160
0161 panel {
0162 compatible = "arm,rtsm-display";
0163
0164 port {
0165 clcd_panel: endpoint {
0166 remote-endpoint = <&clcd_pads>;
0167 };
0168 };
0169 };
0170 ...
