0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/arm,komeda.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm Komeda display processor
0008
0009 maintainers:
0010 - Liviu Dudau <Liviu.Dudau@arm.com>
0011 - Andre Przywara <andre.przywara@arm.com>
0012
0013 description:
0014 The Arm Mali D71 display processor supports up to two displays with up
0015 to a 4K resolution each. Each pipeline can be composed of up to four
0016 layers. It is typically connected to a digital display connector like HDMI.
0017
0018 properties:
0019 compatible:
0020 oneOf:
0021 - items:
0022 - const: arm,mali-d32
0023 - const: arm,mali-d71
0024 - const: arm,mali-d71
0025
0026 reg:
0027 maxItems: 1
0028
0029 interrupts:
0030 maxItems: 1
0031
0032 clock-names:
0033 const: aclk
0034
0035 clocks:
0036 maxItems: 1
0037 description: The main DPU processor clock
0038
0039 "#address-cells":
0040 const: 1
0041
0042 "#size-cells":
0043 const: 0
0044
0045 memory-region:
0046 maxItems: 1
0047 description:
0048 Phandle to a node describing memory to be used for the framebuffer.
0049 If not present, the framebuffer may be located anywhere in memory.
0050
0051 iommus:
0052 description:
0053 The stream IDs for each of the used pipelines, each four IDs for the
0054 four layers, plus one for the write-back stream.
0055 minItems: 5
0056 maxItems: 10
0057
0058 patternProperties:
0059 '^pipeline@[01]$':
0060 type: object
0061 description:
0062 clocks
0063
0064 properties:
0065 reg:
0066 enum: [ 0, 1 ]
0067
0068 clock-names:
0069 const: pxclk
0070
0071 clocks:
0072 maxItems: 1
0073 description: The input reference for the pixel clock.
0074
0075 port:
0076 $ref: /schemas/graph.yaml#/$defs/port-base
0077 unevaluatedProperties: false
0078
0079 additionalProperties: false
0080
0081 required:
0082 - "#address-cells"
0083 - "#size-cells"
0084 - compatible
0085 - reg
0086 - interrupts
0087 - clock-names
0088 - clocks
0089 - pipeline@0
0090
0091 examples:
0092 - |
0093 display@c00000 {
0094 #address-cells = <1>;
0095 #size-cells = <0>;
0096 compatible = "arm,mali-d71";
0097 reg = <0xc00000 0x20000>;
0098 interrupts = <168>;
0099 clocks = <&dpu_aclk>;
0100 clock-names = "aclk";
0101 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
0102 <&smmu 8>,
0103 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
0104 <&smmu 9>;
0105
0106 dp0_pipe0: pipeline@0 {
0107 clocks = <&fpgaosc2>;
0108 clock-names = "pxclk";
0109 reg = <0>;
0110
0111 port {
0112 dp0_pipe0_out: endpoint {
0113 remote-endpoint = <&db_dvi0_in>;
0114 };
0115 };
0116 };
0117
0118 dp0_pipe1: pipeline@1 {
0119 clocks = <&fpgaosc2>;
0120 clock-names = "pxclk";
0121 reg = <1>;
0122
0123 port {
0124 dp0_pipe1_out: endpoint {
0125 remote-endpoint = <&db_dvi1_in>;
0126 };
0127 };
0128 };
0129 };
0130 ...
