0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 # Copyright 2019 BayLibre, SAS
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Amlogic Meson Display Controller
0009
0010 maintainers:
0011 - Neil Armstrong <neil.armstrong@linaro.org>
0012
0013 description: |
0014 The Amlogic Meson Display controller is composed of several components
0015 that are going to be documented below
0016
0017 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
0018 | vd1 _______ _____________ _________________ | |
0019 D |-------| |----| | | | | HDMI PLL |
0020 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
0021 R |-------| |----| Processing | | | | |
0022 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
0023 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
0024 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
0025 M |-------|______|----|____________| |________________| | |
0026 ___|__________________________________________________________|_______________|
0027
0028
0029 VIU: Video Input Unit
0030 ---------------------
0031
0032 The Video Input Unit is in charge of the pixel scanout from the DDR memory.
0033 It fetches the frames addresses, stride and parameters from the "Canvas" memory.
0034 This part is also in charge of the CSC (Colorspace Conversion).
0035 It can handle 2 OSD Planes and 2 Video Planes.
0036
0037 VPP: Video Post Processing
0038 --------------------------
0039
0040 The Video Post Processing is in charge of the scaling and blending of the
0041 various planes into a single pixel stream.
0042 There is a special "pre-blending" used by the video planes with a dedicated
0043 scaler and a "post-blending" to merge with the OSD Planes.
0044 The OSD planes also have a dedicated scaler for one of the OSD.
0045
0046 VENC: Video Encoders
0047 --------------------
0048
0049 The VENC is composed of the multiple pixel encoders
0050 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
0051 - ENCP : Progressive Video Encoder for HDMI
0052 - ENCL : LCD LVDS Encoder
0053 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
0054 tree and provides the scanout clock to the VPP and VIU.
0055 The ENCI is connected to a single VDAC for Composite Output.
0056 The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
0057
0058 properties:
0059 compatible:
0060 oneOf:
0061 - items:
0062 - enum:
0063 - amlogic,meson-gxbb-vpu # GXBB (S905)
0064 - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
0065 - amlogic,meson-gxm-vpu # GXM (S912)
0066 - const: amlogic,meson-gx-vpu
0067 - enum:
0068 - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
0069
0070 reg:
0071 maxItems: 2
0072
0073 reg-names:
0074 items:
0075 - const: vpu
0076 - const: hhi
0077
0078 interrupts:
0079 maxItems: 1
0080
0081 amlogic,canvas:
0082 description: should point to a canvas provider node
0083 $ref: /schemas/types.yaml#/definitions/phandle
0084
0085 power-domains:
0086 maxItems: 1
0087 description: phandle to the associated power domain
0088
0089 port@0:
0090 $ref: /schemas/graph.yaml#/properties/port
0091 description:
0092 A port node pointing to the CVBS VDAC port node.
0093
0094 port@1:
0095 $ref: /schemas/graph.yaml#/properties/port
0096 description:
0097 A port node pointing to the HDMI-TX port node.
0098
0099 "#address-cells":
0100 const: 1
0101
0102 "#size-cells":
0103 const: 0
0104
0105 required:
0106 - compatible
0107 - reg
0108 - interrupts
0109 - port@0
0110 - port@1
0111 - "#address-cells"
0112 - "#size-cells"
0113 - amlogic,canvas
0114
0115 additionalProperties: false
0116
0117 examples:
0118 - |
0119 vpu: vpu@d0100000 {
0120 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
0121 reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
0122 reg-names = "vpu", "hhi";
0123 interrupts = <3>;
0124 #address-cells = <1>;
0125 #size-cells = <0>;
0126 amlogic,canvas = <&canvas>;
0127
0128 /* CVBS VDAC output port */
0129 port@0 {
0130 reg = <0>;
0131
0132 cvbs_vdac_out: endpoint {
0133 remote-endpoint = <&tv_connector_in>;
0134 };
0135 };
0136
0137 /* HDMI TX output port */
0138 port@1 {
0139 reg = <1>;
0140
0141 hdmi_tx_out: endpoint {
0142 remote-endpoint = <&hdmi_tx_in>;
0143 };
0144 };
0145 };
