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0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 # Copyright 2019 BayLibre, SAS
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007 
0008 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
0009 
0010 maintainers:
0011   - Neil Armstrong <neil.armstrong@linaro.org>
0012 
0013 allOf:
0014   - $ref: /schemas/sound/name-prefix.yaml#
0015 
0016 description: |
0017   The Amlogic Meson Synopsys Designware Integration is composed of
0018   - A Synopsys DesignWare HDMI Controller IP
0019   - A TOP control block controlling the Clocks and PHY
0020   - A custom HDMI PHY in order to convert video to TMDS signal
0021    ___________________________________
0022   |            HDMI TOP               |<= HPD
0023   |___________________________________|
0024   |                  |                |
0025   |  Synopsys HDMI   |   HDMI PHY     |=> TMDS
0026   |    Controller    |________________|
0027   |___________________________________|<=> DDC
0028 
0029   The HDMI TOP block only supports HPD sensing.
0030   The Synopsys HDMI Controller interrupt is routed through the
0031   TOP Block interrupt.
0032   Communication to the TOP Block and the Synopsys HDMI Controller is done
0033   via a pair of dedicated addr+read/write registers.
0034   The HDMI PHY is configured by registers in the HHI register block.
0035 
0036   Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
0037   selects either the ENCI encoder for the 576i or 480i formats or the ENCP
0038   encoder for all the other formats including interlaced HD formats.
0039 
0040   The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
0041   DVI timings for the HDMI controller.
0042 
0043   Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
0044   HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
0045   audio source interfaces.
0046 
0047 properties:
0048   compatible:
0049     oneOf:
0050       - items:
0051           - enum:
0052               - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
0053               - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
0054               - amlogic,meson-gxm-dw-hdmi # GXM (S912)
0055           - const: amlogic,meson-gx-dw-hdmi
0056       - enum:
0057           - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
0058 
0059   reg:
0060     maxItems: 1
0061 
0062   interrupts:
0063     maxItems: 1
0064 
0065   clocks:
0066     minItems: 3
0067 
0068   clock-names:
0069     items:
0070       - const: isfr
0071       - const: iahb
0072       - const: venci
0073 
0074   resets:
0075     minItems: 3
0076 
0077   reset-names:
0078     items:
0079       - const: hdmitx_apb
0080       - const: hdmitx
0081       - const: hdmitx_phy
0082 
0083   hdmi-supply:
0084     description: phandle to an external 5V regulator to power the HDMI logic
0085 
0086   port@0:
0087     $ref: /schemas/graph.yaml#/properties/port
0088     description:
0089       A port node pointing to the VENC Input port node.
0090 
0091   port@1:
0092     $ref: /schemas/graph.yaml#/properties/port
0093     description:
0094       A port node pointing to the TMDS Output port node.
0095 
0096   "#address-cells":
0097     const: 1
0098 
0099   "#size-cells":
0100     const: 0
0101 
0102   "#sound-dai-cells":
0103     const: 0
0104 
0105   sound-name-prefix: true
0106 
0107 required:
0108   - compatible
0109   - reg
0110   - interrupts
0111   - clocks
0112   - clock-names
0113   - resets
0114   - reset-names
0115   - port@0
0116   - port@1
0117   - "#address-cells"
0118   - "#size-cells"
0119 
0120 additionalProperties: false
0121 
0122 examples:
0123   - |
0124     hdmi_tx: hdmi-tx@c883a000 {
0125         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
0126         reg = <0xc883a000 0x1c>;
0127         interrupts = <57>;
0128         resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
0129         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
0130         clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
0131         clock-names = "isfr", "iahb", "venci";
0132         #address-cells = <1>;
0133         #size-cells = <0>;
0134 
0135         /* VPU VENC Input */
0136         hdmi_tx_venc_port: port@0 {
0137             reg = <0>;
0138 
0139             hdmi_tx_in: endpoint {
0140                 remote-endpoint = <&hdmi_tx_out>;
0141             };
0142         };
0143 
0144         /* TMDS Output */
0145         hdmi_tx_tmds_port: port@1 {
0146              reg = <1>;
0147 
0148              hdmi_tx_tmds_out: endpoint {
0149                  remote-endpoint = <&hdmi_connector_in>;
0150              };
0151         };
0152     };